Nevion ARC-SD-XMUX4 - Manual (Page 7)

ARC-SD-XMUX4 Rev. B
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3 Description
3.1 Data paths
The SD-SDI input selected from the optical or electrical input is equalized, re-clocked and de-
serialized and transferred to a processing unit (FPGA). In the FPGA the signal is sent
through a de-glitcher that cleans up erroneous video lines, for instance due to switching.
After the de-glitcher the video is sent to the Audio de-embedders, where audio is split from
the video.
3.1.1 Audio data path
The stereo audio channels from the de-embedder are sent to an audio store buffer. The
audio is fetched from the audio store buffer after the user specified delay. It is then sent to
the Audio matrix.
Two other sources are available in the audio matrix: A 1 kHz stereo sine tone and a
generated black sound which is a legal audio stream with muted audio.
Depending of how many of the configurable AES I/Os have been designated as inputs, there
may also be up to four AES inputs available in the matrix.
Outputs with missing inputs are routed to a fallback signal. The fallback signal may be
silence or the tone generator.
Each output from the matrix is sent to an Audio Processing Block where channels can be
processed or rearranged within the channel pair.
Finally, eight stereo pairs are routed to the Audio Embedder. Depending on how many of the
four AES I/Os have been designated as outputs, up to four stereo pairs are also routed the
AES outputs.
3.1.2 Video data path
The video is routed to an aspect ratio converter block and the resulting SD video is passed to
a Frame synchronizer block.
An internal video generator can be switched in as a fallback source if the input video is
missing.
The audio is re-embedded and the video then passes through a Video processing block with
an integrated Legalizer, before entering an EDH processing block. Embedding of the EDH
packet is configurable.
The parallel video is sent out from the FPGA and into a serializer that re-clocks the data and
sends the SDI to a buffered output switch.
The output switch is used to bypass the video processing core so that DVB-ASI may pass
through the module. The switch selects between the FPGA output (Processed mode) and
video that has only been re-clocked (Through mode).