Epson S1C88650 - Manual (Page 54)

46 EPSON S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)
K03
Data bus
K02
K00
Input comparison
register KCP00
Address
K01
Input port
K00D
Chattering-eliminate
circuit
Check time setup register
CTK00L–CTK02L
Interrupt
priority level
judgement
circuit
Interrupt
request
Interrupt factor
flag FK00
Address
Address
Address
Address
Interrupt
priority
register
PK00, PK01
Interrupt enable
register EK00
K07
K06
K04
Input comparison
register KCP04
Address
K05
Chattering-eliminate
circuit
Check time setup register
CTK00H–CTK02H
Interrupt factor
flag FK04
Address
Address
Address
Interrupt enable
register EK04
Divider
f OSC1
Input port
K04D
OSC1
oscillation circuit
Divider
f OSC3 OSC3
oscillation circuit
Table 5.5.4.1 Setting the input level check time
CTK02x
1
1
1
1
0
0
0
0
CTK01x
1
1
0
0
1
1
0
0
CTK00x
1
0
1
0
1
0
1
0
Check time (
∗
)
4/f OSC3 (2
µ
s)
2/f OSC3 (1
µ
s)
1/f OSC3 (0.5
µ
s)
4096/f OSC1 (128 ms)
2048/f OSC1 (64 ms)
512/f OSC1 (16 ms)
128/f OSC1 (4 ms)
None –
∗:
When OSC1 = 32 kHz, OSC3 = 2 MHz
Notes: • Be sure to disable interrupts before
changing the contents of the CTK0x
register. Unnecessary interrupts may
occur if the register is changed when the
corresponding input port interrupts have
been enabled by the interrupt enable
register EK0x.
• The chattering-eliminate check time
means the maximum pulse width that can
be eliminated. The valid interrupt input
needs a pulse width of the set check time
(minimum) to twice that of the check time
(maximum).
• The internal signal may oscillate if the rise /
fall time of the input signal is too long
because the input signal level transition to
the threshold level duration of time is too
long. This causes the input interrupt to
malfunction, therefore setup the input signal
so that the rise/fall time is 25 nsec or less.
Fig. 5.5.4.1 Configuration of input interrupt circuit