Epson S1C88650 - Manual (Page 86)

78 EPSON S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
RXTRG: 00FF49H•D3
Functions as the receiving start trigger or prepara-
tion for the following data receiving and the opera-
tion status indicator (during receiving/during stop).
When "1" is read: During receiving
When "0" is read: During stop
When "1" is written: Receiving start/following
data receiving preparation
When "0" is written: Invalid
RXTRG has a slightly different operation in the clock
synchronous system and the asynchronous system.
The RXTRG in the clock synchronous system, is
used as the trigger for the receiving start.
Writes "1" into RXTRG to start receiving at the
point where the receive data has been read and the
following receive preparation has been done. (In
_________
the slave mode, SRDY becomes "0" at the point
where "1" has been written into into the RXTRG.)
RXTRG is used in the asynchronous system for
preparation of the following data receiving. Reads
the received data located in the received data buffer
and writes "1" into RXTRG to inform that the
received data buffer has shifted to empty. When "1"
has not been written to RXTRG, the overrun error
flag OER is set to "1" at the point where the follow-
ing receiving has been completed. (When the
receiving has been completed between the opera-
tion to read the received data and the operation to
write "1" into RXTRG, an overrun error occurs.)
In addition, RXTRG can be read as the status. In
either clock synchronous mode or asynchronous
mode, when RXTRG is set to "1", it indicates
receiving operation and when set to "0", it indicates
that receiving has stopped.
At initial reset, RXTRG is set to "0" (during stop).
TRXD0–TRXD7: 00FF4AH
During transmitting
Write the transmitting data into the transmit shift
register.
When "1" is written: HIGH level
When "0" is written: LOW level
Write the transmitting data prior to starting
transmitting.
In the case of continuous transmitting, wait for the
transmitting complete interrupt, then write the data.
The TRXD7 becomes invalid for the asynchronous
7-bit mode.
Converted serial data for which the bits set at "1" as
HIGH (V
DD ) level and for which the bits set at "0"
as LOW (V SS ) level are output from the SOUT
terminal.
During receiving
Read the received data.
When "1" is read: HIGH level
When "0" is read: LOW level
The data from the received data buffer can be read out.
Since the sift register is provided separately from
this buffer, reading can be done during the receive
operation in the asynchronous mode. (The buffer
function is not used in the clock synchronous mode.)
Read the data after waiting for the receiving
complete interrupt.
When performing parity check in the asynchronous
7-bit mode, "0" is loaded into the 8th bit (TRXD7)
that corresponds to the parity bit.
The serial data input from the SIN terminal is level
converted, making the HIGH (V
DD ) level bit "1" and
the LOW (V SS ) level bit "0" and is then loaded into
this buffer.
At initial reset, the buffer content is undefined.
OER: 00FF49H•D4
Indicates the generation of an overrun error.
When "1" is read: Error
When "0" is read: No error
When "1" is written: Reset to "0"
When "0" is written: Invalid
OER is an error flag that indicates the generation of
an overrun error and becomes "1" when an error
has been generated.
An overrun error is generated when the receiving
of data has been completed prior to the writing of
"1" to RXTRG in the asynchronous mode.
OER is reset to "0" by writing "1".
At initial reset and when RXEN is "0", OER is set to
"0" (no error).
PER: 00FF49H•D5
Indicates the generation of a parity error.
When "1" is read: Error
When "0" is read: No error
When "1" is written: Reset to "0"
When "0" is written: Invalid
PER is an error flag that indicates the generation of
a parity error and becomes "1" when an error has
been generated.
When a parity check is performed in the asynchro-
nous mode, if data that does not match the parity is
received, a parity error is generated.
PER is reset to "0" by writing "1".
At initial reset and when RXEN is "0", PER is set to
"0" (no error).