Document Outline

• 1. General description
• 2. Features
• 3. Applications
• 4. Ordering information
• 5. Block diagram
• 6. Pinning information
  • 6.1 Pinning
  • 6.2 Pin description
• 7. Functional description
  • 7.1 General
  • 7.2 Internal oscillator
  • 7.3 Registers
    • 7.3.1 Direct registers
      • 7.3.1.1 The Status register, I2CSTA (A1=0, A0=0)
      • 7.3.1.2 The Indirect Pointer register, INDPTR (A1=0, A0=0)
      • 7.3.1.3 The I2C-bus Data register, I2CDAT (A1=0, A0=1)
      • 7.3.1.4 The Control register, I2CCON (A1=1, A0=1)
      • 7.3.1.5 The indirect data field access register, INDIRECT (A1 = 1, A0=0)
    • 7.3.2 Indirect registers
      • 7.3.2.1 The Byte Count register, I2CCOUNT (indirect address 00h)
      • 7.3.2.2 The Own Address register, I2CADR (indirect address 01h)
      • 7.3.2.3 The Clock Rate registers, I2CSCLL and I2CSCLH (indirect addresses 02h and 03h)
      • 7.3.2.4 The Time-out register, I2CTO (indirect address 04h)
      • 7.3.2.5 The Parallel Software Reset register, I2CPRESET (indirect address 05h)
      • 7.3.2.6 The I2C-bus mode register, I2CMODE (indirect address 06h)
• 8. PCA9665 modes
  • 8.1 Configuration modes
    • 8.1.1 Byte mode
    • 8.1.2 Buffered mode
  • 8.2 Operating modes
  • 8.3 Byte mode
    • 8.3.1 Master Transmitter Byte mode
    • 8.3.2 Master Receiver Byte mode
    • 8.3.3 Slave Receiver Byte mode
    • 8.3.4 Slave Transmitter Byte mode
  • 8.4 Buffered mode
    • 8.4.1 Master Transmitter Buffered mode
    • 8.4.2 Master Receiver Buffered mode
    • 8.4.3 Slave Receiver Buffered mode
    • 8.4.4 Slave Transmitter Buffered mode
  • 8.5 Buffered mode examples
    • 8.5.1 Buffered Master Transmitter mode of operation
    • 8.5.2 Buffered Master Receiver mode of operation
    • 8.5.3 Buffered Slave Transmitter mode
    • 8.5.4 Buffered Slave Receiver mode
    • 8.5.5 Example: Read 128 bytes in two 64-byte sequences of an EEPROM (I2C-busaddress=A0h for wr...
  • 8.6 I2CCOUNT register
  • 8.7 Acknowledge management (I2C-bus addresses and data) in Byte and Buffered modes
  • 8.8 Miscellaneous states
    • 8.8.1 I2CSTA=F8h
    • 8.8.2 I2CSTA=00h
    • 8.8.3 I2CSTA=70h
    • 8.8.4 I2CSTA=78h
  • 8.9 Some special cases
    • 8.9.1 Simultaneous repeated START conditions from two masters
    • 8.9.2 Data transfer after loss of arbitration
    • 8.9.3 Forced access to the I2C-bus
    • 8.9.4 I2C-bus obstructed by a LOW level on SCL or SDA
    • 8.9.5 Bus error
  • 8.10 Power-on reset
  • 8.11 Reset
  • 8.12 I2C-bus timing diagrams, Unbuffered mode
  • 8.13 I2C-bus timing diagrams, Buffered mode
• 9. Characteristics of the I2C-bus
  • 9.1 Bit transfer
    • 9.1.1 START and STOP conditions
  • 9.2 System configuration
  • 9.3 Acknowledge
• 10. Application design-in information
  • 10.1 Specific applications
  • 10.2 Add I2C-bus port
  • 10.3 Add additional I2C-bus ports
  • 10.4 Convert 8bits of parallel data into I2C-bus serial data stream
• 11. Limiting values
• 12. Static characteristics
• 13. Dynamic characteristics
• 14. Test information
• 15. Package outline
• 16. Handling information
• 17. Soldering
  • 17.1 Introduction
  • 17.2 Through-hole mount packages
    • 17.2.1 Soldering by dipping or by solder wave
    • 17.2.2 Manual soldering
  • 17.3 Surface mount packages
    • 17.3.1 Reflow soldering
    • 17.3.2 Wave soldering
    • 17.3.3 Manual soldering
  • 17.4 Package related soldering information
• 18. Abbreviations
• 19. Revision history
• 20. Legal information
  • 20.1 Data sheet status
  • 20.2 Definitions
  • 20.3 Disclaimers
  • 20.4 Trademarks
• 21. Contact information
• 22. Contents