NXP Semiconductors PCA9665 - Manual (Page 6)

PCA9665_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 7 December 2006 6 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I 2 C-bus controller
7. Functional description
7.1 General
The PCA9665 acts as an interface device between standard high-speed parallel buses
and the serial I
2 C-bus. On the I 2 C-bus, it can act either as a master or slave. Bidirectional
data transfer between the I 2 C-bus and the parallel-bus microcontroller is carried out on a
byte or buffered basis, using either an interrupt or polled handshake.
7.2 Internal oscillator
The PCA9665 contains an internal 28.5 MHz oscillator which is used for all I 2 C-bus timing.
The oscillator requires up to 550 µ s to start-up after ENSIO bit is set to ‘1’.
7.3 Registers
The PCA9665 contains eleven registers which are used to configure the operation of the
device as well as to send and receive serial data. There are four registers that can be
accessed directly and seven registers that are accessed indirectly by setting a register
pointer.
The four direct registers are selected by setting pins A0 and A1 to the appropriate logic
levels before a read or write operation is executed on the parallel bus.
The seven indirect registers require that the INDPTR (indirect register pointer, one of the
four direct registers described above) is initially loaded with the address of the register in
the indirect address space before a read or write is performed to the INDIRECT data field.
For example, in order to write to the indirectly addressed I2CSCLL register, the INDPTR
register should be loaded with 02h by performing a write to the direct INDPTR register
(A1 = 0, A0 = 0). Then the I2CSCLL register can be programmed by writing to the
INDIRECT data field (A1 = 1, A0 = 0) in the direct address space. Register mapping is
described in
Table 3 , Table 4 and Figure 6 .
Remark: Do not write to any I 2 C-bus registers while the I 2 C-bus is busy and the PCA9665
is in master or addressed slave mode.
[1] See Section 8.10 “Power-on reset” for more detail.
Table 3. Direct register selection by setting A0 and A1
Register name Register function A1 A0 Read/Write Default
I2CSTA status 0 0 R F8h
INDPTR indirect register pointer 0 0 W 00h
I2CDAT data 0 1 R/W 00h
I2CCON control 1 1 R/W 00h [1]
INDIRECT indirect data field
access 1 0 R/W 00h