Pca9665 – NXP Semiconductors PCA9665 User Manual
Page 88
PCA9665_2
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 7 December 2006
88 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
Modifications:
(continued)
•
, sub-section “Bus timing”:
– changed Min value for t
h(A)
from 7 ns to 13 ns
– changed Min value for t
w(RDL)
from 7 ns to 20 ns
– changed Min value for t
w(WRL)
from 7 ns to 20 ns
– changed Min value for t
su(Q)
from 7 ns to 12 ns
– changed Min value for t
w(RDH)
from 12 ns to 18 ns
– changed Min value for t
w(WRH)
from 12 ns to 18 ns
•
Table 50 “Dynamic characteristics (2.5 volt)
:
– added sub-sections “Initialization timing” and “Serial interface initialization timing”
– sub-section “INT timing”: changed t
as(int)
from (Typ) “<tbd>” to (Max) “550 ns”
– sub-section “INT timing”: changed t
das(int)
from (Typ) “<tbd>” to (Max) “20 ns”
•
, sub-section “Bus timing”:
– changed Min value for t
h(A)
from 9 ns to 13 ns
– changed Min value for t
w(RDL)
from 9 ns to 20 ns
– changed Min value for t
w(WRL)
from 9 ns to 20 ns
– changed Min value for t
su(Q)
from 8 ns to 12 ns
– changed Min value for t
w(RDH)
from 12 ns to 18 ns
– changed Min value for t
w(WRH)
from 12 ns to 18 ns
•
•
Figure 38 “Bus timing (read cycle)”
modified
•
Added (new)
Figure 39 “Parallel bus timing (write cycle)”
•
C-bus frequency and timing specifications”
:
– t
VD;ACK
(Min) changed: (Standard-mode) from 0.3
µ
s to 0.05
µ
s; (Fast-mode) from 0.1
µ
s to
0.05
µ
s
– t
VD;DAT
(Min) changed: (Fast-mode Plus) from “<tbd>” to “50 ns”
– t
SP
(Max) changed: (Fast-mode Plus) from “<tbd>” to “50 ns”
•
Added (new)
•
Figure 43 “Test circuitry for switching times”
modified (at switch, “6.0 V” changed to “V
DD
×
2”
•
: modified test t
d(DV)
changed S1 value from “6 V” to “V
DD
×
2”
•
Added (new)
Figure 44 “Test circuitry for open-drain switching times”
.
PCA9665_1
20060807
Objective data sheet
-
-
Table 58.
Revision history
…continued
Document ID
Release date
Data sheet status
Change notice
Supersedes