NXP Semiconductors PCA9665 - Manual (Page 12)

PCA9665_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 7 December 2006 12 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I 2 C-bus controller
7.3.2 Indirect registers
7.3.2.1 The Byte Count register, I2CCOUNT (indirect address 00h)
The I2CCOUNT register is an 8-bit read/write register. It contains the number of bytes that
have been stored in Master/Slave Buffered Receiver mode, and the number of bytes to be
sent in Master/Slave Buffered Transmitter mode. Bit 7 is the last byte control bit and
applies to the Master/Slave Buffered Receiver mode only. The data in the I2CCOUNT
register is relevant only in Buffered mode (MODE = 1) and should not be used (read or
written) in Byte mode (MODE = 0).
7.3.2.2 The Own Address register, I2CADR (indirect address 01h)
I2CADR is an 8-bit read/write register. It is not affected by the bus controller hardware.
The content of this register is irrelevant when the bus controller is in a master mode. In the
slave modes, the seven most significant bits must be loaded with the microcontroller's own
slave address and the least significant bit determines if the General Call address will be
recognized or not.
Remark: AD[7:1] must be different from the General Call address (000 0000) for proper
device operation.
Table 13. I2CCOUNT - Byte Count register (indirect address 00h) bit allocation
7 6 5 4 3 2 1 0
LB BC6 BC5 BC4 BC3 BC2 BC1 BC0
Table 14. I2CCOUNT - Byte Count register (indirect address 00h) bit description
Bit Symbol Description
7 LB Last Byte control bit. Master/Slave Buffered Receiver mode only.
LB = 1: PCA9665 does not acknowledge the last received byte.
LB = 0: PCA9665 acknowledges the last received byte. A future bus
transaction must complete the read sequence by not acknowledging the last
byte.
6:0 BC[6:0] Number of bytes to be read or written (up to 68 bytes). If BC[6:0] is equal to 0 or
greater than 68 (44h), no bytes will be read or written and an interrupt is
immediately generated after writing to the I2CCON register (in Buffered mode
only).
Table 15. I2CADR - Address register (indirect address 01h) bit allocation
7 6 5 4 3 2 1 0
AD7 AD6 AD5 AD4 AD3 AD2 AD1 GC
Table 16. I2CADR - Address register (indirect address 01h) bit description
Bit Symbol Description
7:1 AD[7:1] Own slave address. The most significant bit corresponds to the first bit received
from the I
2 C-bus after a START condition. A logic 1 in I2CADR corresponds to a
HIGH level on the I 2 C-bus, and a logic 0 corresponds to a LOW level on the bus.
0 GC General Call.
GC = 1: General Call address (00h) is recognized.
GC = 0: General Call address (00h) is ignored.