NXP Semiconductors PCA9665 - Manual (Page 16)

PCA9665_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 7 December 2006 16 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I 2 C-bus controller
8. PCA9665 modes
8.1 Configuration modes
Byte mode and Buffered mode are selected using the MODE bit in I2CCON register:
MODE = 0: Byte mode
MODE = 1: Buffered mode
8.1.1 Byte mode
The Byte mode allows communication on a single command basis. Only one specific
command is executed at a time and the Status Register is updated once this single
command has been performed. A command can be a START, a STOP, a Byte Write, a
Byte Read, and so on.
8.1.2 Buffered mode
The Buffered mode allows several instructions to be executed before an Interrupt is
generated and before the I2CSTA register is updated. This allows the microcontroller to
request a sequence, up to 68 bytes in a single transmission and lets the PCA9665
perform it without having to access the Status Register and the Control Register each time
a single command is performed. The microcontroller can then perform other tasks while
the PCA9665 performs the requested sequence.
The number of bytes that needs to be sent from the internal buffer (Transmitter mode) or
received into the internal buffer (Receiver mode) is defined in the indirectly addressed
I2CCOUNT Register (BC[6:0]). Up to 68 bytes can be sent or received.
8.2 Operating modes
The four operating modes are:
• Master Transmitter
• Master Receiver
• Slave Receiver
• Slave Transmitter
Each mode can be used on a byte basis (Byte mode) or in an up to 68-byte buffer basis
(Buffered mode).
Data transfers in each mode of operation are shown in Figure 7 through Figure 10 . These
figures contain the following abbreviations:
S — START condition
SLA — 7-bit slave address
R — Read bit (HIGH level at SDA)
W — Write bit (LOW level at SDA)
A — Acknowledge bit (LOW level at SDA)
A — Not acknowledge bit (HIGH level at SDA)
Data — 8-bit data byte