Maxtor D540X-4K - Manual (Page 77)

ATA Bus Interface and ATA Commands
Maxtor D540X-4K 20.4/40.0/60.0/80.0 GB AT 6-15
CE – Cache Enable (Byte 32, Bit 0): When set to 1, this bit indicates that the drive
will activate caching on all READ commands. With the CE bit set to 0, the drive will
disable caching and use the RAM only as a transfer buffer. The default setting is 1.
Error Recovery Parameters
AWRE – Automatic Write Reallocation Enabled (Byte 36, Bit 7): When set
to 1, indicates that the drive will enable automatic reallocation of bad blocks.
Automatic Write Reallocation is similar to the function of Automatic Read
Reallocation, but is initiated by the drive when a defective block has become
inaccessible for writing. An AWRE bit set to 0 indicates that the Maxtor D540X-4K
20.4/40.0/60.0/80.0 GB AT drives will not automatically reallocate bad blocks. The
default setting is 1.
ARR – Automatic Read Reallocation (Byte 36, Bit 6): When set to 1, this bit
indicates that the drive will enable automatic reallocation of bad sectors. The drive
initiates reallocation when the ARR bit is set to 1 and the drive encounters a hard
error—that is, if the triple-burst ECC algorithm is invoked. The default setting is 1.
When the ARR bit is set to 0, the drive will not perform automatic reallocation of
bad sectors. If RC (byte 36, bit 4) is 1, the drive ignores this bit. The default value is 1.
RC – Read Continuous (Byte 36, Bit 4): When set to 1, this bit instructs the drive
to transfer data of the requested length without adding delays to increase data
integrity—that is, delays caused by the drive’s error-recovery procedures. With RC
set to 1 to maintain a continuous flow of data and avoid delays, the drive may send
data that is erroneous. When the drive ignores an error, it does not post the error. The
RC bit set to 0 indicates that potentially time-consuming operations for error recovery
are acceptable during data transfer. The default setting is 0.
EEC – Enable Early Correction (Byte 36, Bit 3): When set to 1, this bit indicates
that the drive will use its ECC algorithm if it detects two consecutive equal, nonzero
error syndromes. The drive will not perform rereads before applying correction, unless
it determines that the error is uncorrectable. An EEC bit set to 0 indicates that the
drive will use its normal recovery procedure when an error occurs: rereads, followed
by error correction. If the RC bit (byte 36, bit 4) is set to 1, the drive ignores the EEC
bit. The default setting is 0.
SilentMode (Byte 36, Bit 2): When set to 1, this bit indicates that the drive’s
acoustic emanations will be reduced.
DCR – Disable Correction (Byte 36, Bit 0): When set to 1, this bit indicates that
all data will be transferred without correction, even if it would be possible to correct
the data. A DCR bit set to 0 indicates that the data will be corrected if possible. If the
data is uncorrectable, it will be transferred without correction, though the drive will
attempt rereads. If RC (byte 36, bit 4) is set to 1, the drive ignores this bit. The default
setting is 0. The drive will post all errors, whether DCR is set to 0 or 1.
NUMBER OF RETRIES (Byte 37) : This byte specifies the number of times that
the drive will attempt to recover from data errors by rereading the data, before it will
apply correction. The drive performs rereads before ECC correction—unless EEC
(byte 36, bit 3) is set to 1, enabling early correction. The default is eight.
ECC CORRECTION SPAN (Byte 38): This byte specifies the maximum number
of 10-bit symbols that can be corrected using ECC. The default value for this byte is
20h or 32 decimal.