Interphase Tech CONDOR 4221 - Manual (Page 70)

Chapter 3 - MACSI Host Interface
58
Master Control Register (MCR)
The MCR provides the host with infrequently used services. These bits are both set and cleared by the host. The
controller clears these bits on power up, and does not alter them at any other time.
Table 3-4. Master Control Register
Start queue mode (SQM)
This bit is provided for compatibility with the 4207 Eagle MACSI interface. When the host sets this bit, the
controller returns a Command Complete interrupt, and then sets the QMS (Queue Mode Started) with all
subsequent returned commands. Setting this bit produces no operational effect on the controller.
Controller Reset (RST)
This bit generates a controller reset. To ensure proper operation, the host system must set the bit for at least
50 microseconds, and then clear it. Use of this bit should not be necessary under normal operation, but
typically only used during initialization.
Sysfail Enable (SFEN)
This bit is for backward compatibility to the 4207 Eagle. This bit does not perform any function. Use jumper
J14, Pins 3-4 for Sysfail options. (See page 18)
Master Control Register
Addr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x004 SFEN RST SQM