Iopb address command tag work queue number, Offboard command queue entry, Queue entry control register (qecr) – Interphase Tech CONDOR 4221 User Manual

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Chapter 3 - MACSI Host Interface

60

Fetch offboard (FOB)

Setting this bit makes the Command Queue entry an offboard entry. Please see the following section for
details.

Fetch offboard in progress (FIP)

This bit is used internally by the controller. It’s value should not be used by the host driver.

IOPB Address

This field contains a pointer to the IOPB for the command being issued, and is specified as an offset, in bytes, from the
start of Short I/O space. The space occupied by the IOPB will be available for re-use as soon as the controller clears
the Go bit, indicating that the command has been received.

Command Tag

This field is returned unchanged to the host upon completion of the command, and may be used to uniquely identify
the returned command. Typically, the host driver would place a pointer to a control structure associated with the
command in this field. The controller does not use the value in this field in any way.

Work Queue Number

This field is not currently used, though the value entered will be returned to the host.

Offboard Command Queue Entry

The following fields are defined for an offboard Command Queue entry.

Table 3-7. Offboard Command Queue Entry

Queue Entry Control Register (QECR)

The QECR field in the offboard entry is identical to the onboard version, except that the Fetch Offboard bit is set.

Offboard Command Queue Entry

Offst

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0x00

Queue Entry Control Register

0x01

Dma Transfer Control Word

0x02

Host Address (MSW)

0x03

Host Address (LSW)

0x04

Offboard Transfer Length

Work Queue Number

0x05

Reserved

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