Interphase Tech CONDOR 4221 - Manual (Page 92)

Chapter 3 - MACSI Host Interface
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Abort Report (AR)
Setting this bit causes commands aborted with either the AA or the AN bit to be reported back to the host with
the appropriate error code set. Setting this bit has no effect on pending receives for particular ports aborted
via the Abort Pending bit in the MAC Status/Control field.
Setting all three of these bits (AA, AN, AR) will cause all pending receives posted for all ports, plus all non-
designated pending receives to be returned to the host with the appropriate error set.
Return Status
Full error return status details will be available after the module level design is complete.
Buffer address
This field contains the address of the 6-byte Individual Address when the command is used to set the station address,
or a list of possible addresses when setting up Multiple Individual Address or Multicast Address filtering. Otherwise
the contents of this field are ignored. With the correct Memory Type specified in the DMA Control Word (bit 9 = 0,
bit 8 = 0), this value could be an offset into Short I/O. The contents of the memory location specified in this way will
be reserved for the controllers use, and not available to the host, until the IOPB is returned. Writing additional
information into this field while the controller is processing the IOPB may cause undefined behavior.
Transfer size
This field contains the size in bytes of the data to be transferred from the location specified above.
MAC status/control
This field provides a general set of MAC level functions, which drivers can use to control the particular port without
any reference to the actual Ethernet control chip used on the controller. Drivers using these functions will be portable
to other Interphase Ethernet controllers employing this same MACSI host interface, though they may use different
front end chips. Programs, such as diagnostics and specialized network monitoring programs, can use the following
two fields to obtain direct access to more specialized functions provided by the particular Ethernet control chips
employed.
Table 3-24. MAC Status / Control
Initialize MAC (IM)
Setting this bit (along with the SM bit in the Command Options word) resets the port. This sets all
management counters for the port to zero, resets the physical interface circuitry, and aborts any pending
receives. Without the Enable MAC bit set, neither transmits nor receives will be active, and the port will
respond only to control commands issued through the Control MAC IOPB.
MAC Status/Control
Offst 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x0B TDR LPB MC PM IA AR AP EM IM