Gpsr0 bit definitions -10, Gpsr1 bit definitions -10 – Intel PXA255 User Manual
Page 114
4-10
Intel® PXA255 Processor Developer’s Manual
System Integration Unit
When a GPIO is configured as an output, the state of the pin can be controlled by writing to either
the GPSR or GPCR. An output pin is set high by writing a one to its corresponding bit within the
GPSR. To clear an output pin, a one is written to the corresponding bit within the GPCR. GPSR
and GPCR are write-only registers. Reads return unpredictable values.
Writing a zero to any of the GPSR or GPCR bits has no effect on the state of the pin. Writing a one
to a GPSR or GPCR bit corresponding to a pin that is configured as an input is effective only after
the pin is configured as an output. Reserved bits must be written with zeros and reads must be
ignored.
, and
show the bit definitions of GPSR0, GPSR1, and GPSR2.
, and
show the bit definitions of GPCR0, GPCR1, and GPCR2.
Table 4-9. GPSR0 Bit Definitions
Physical Address
0x40E0_0018
GPSR0
System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
PS3
1
PS3
0
PS2
9
PS2
8
PS2
7
PS2
6
PS2
5
PS2
4
PS2
3
PS2
2
PS2
1
PS2
0
PS1
9
PS1
8
PS1
7
PS1
6
PS1
5
PS1
4
PS1
3
PS1
2
PS1
1
PS1
0
PS9
PS8
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
<31:0>
PS[x]
GPIO Pin ‘x’ Output Pin Set (where x= 0 through 31).
0 – Pin level unaffected.
1 – If pin configured as an output, set pin level high (one).
Table 4-10. GPSR1 Bit Definitions
Physical Address
0x40E0_001C
GPSR1
System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
PS
63
PS
62
PS
61
PS
60
PS
59
PS
58
PS
57
PS
56
PS
55
PS
54
PS
53
PS
52
PS
51
PS
50
PS
49
PS
48
PS
47
PS
46
PS
45
PS
44
PS
43
PS
42
PS
41
PS
40
PS
39
PS
38
PS
37
PS
36
PS
35
PS
34
PS
33
PS
32
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
<31:0>
PS[x]
GPIO Pin ‘x’ Output Pin Set (where x= 32 through 63).
0 – Pin level unaffected.
1 – If pin configured as an output, set pin level high (one).