Intel PXA255 - Manual (Page 72)

3-10 Intel® PXA255 Processor Developer’s Manual
Clocks and Power Manager
Do not confuse the CCLKCFG Register, which is in Coprocessor 14, with the CCCR (See
Section 3.6.1 ), which is in the processor’s Clocks and Power Manager.
3.4.5.2 Behavior in Turbo Mode
The processor’s behavior in Turbo Mode is identical to its behavior in Run Mode, except that the
processor’s clock frequency relative to the memory and peripherals is increased by N, the value in
the CCCR (see Section 3.6.1 ). Turbo mode is intended for use during peak processing, when there
are very few accesses to external memory. The higher Core to external memory clock ratio
increases the relative delay for each external memory access. This increased delay lowers the
processor’s power efficiency. For optimum performance, software must load applications in the
caches in Run Mode and execute them in Turbo Mode.
3.4.5.3 Exiting Turbo Mode
To exit Turbo Mode, software clears the TURBO bit in the CCLKCFG Register. After software
clears the TURBO bit, the CPU waits for all instructions in the pipeline to complete. When the
instructions are completed, the CPU enters Run Mode.
Other bits in the CCLKCFG may be set or cleared in the write that clears CCLKCFG [TURBO].
All other bits in the register take precedence over Turbo Mode, so the new mode’s proper sequence
is followed.
Idle, Sleep, Frequency Change Sequence, and Reset have precedence over Turbo Mode and cause
the processor to exit Turbo Mode. When the CPU exits of one of these modes, it enters either Run
or Turbo Mode, based on the state of CCLKCFG [TURBO].
3.4.6 Idle Mode
Idle Mode allows the user to stop the CPU core clock during periods of processor inactivity and
continue to monitor on- and off-chip interrupt service requests. Idle mode does not change clock
generation, so when an interrupt occurs the CPU is quickly reactivated in the state that preceded
Idle Mode.
During Idle mode these resources are active:
• System unit modules (real-time clock, operating system timer, interrupt controller, general-
purpose I/O, and clocks and power manager)
• Peripheral unit modules (DMA controller, LCD controller, and all other peripheral units)
• Memory Controller resources
3.4.6.1 Entering Idle Mode
During Idle Mode, the clocks to the CPU core stop. All critical applications must be finished and
peripherals must be set up to generate interrupts when they require CPU attention. To enter the Idle
Mode, software selects Idle Mode in PWRMODE[M] (See
Section 3.7.2 ). An interrupt
immediately aborts Idle Mode and normal processing resumes. After software selects Idle Mode,
the CPU waits until all instructions in the pipeline are completed. When the instructions are
completed, the CPU clock stops and Idle Mode begins. In Idle Mode, interrupts are recognized as
wake-up sources.