Intel PXA255 - Manual (Page 312)

8-2 Intel® PXA255 Processor Developer’s Manual
Synchronous Serial Port Controller
SSPEXTCLK is an external clock (input through GPIO27) that replaces the standard 3.6864 MHz
clock used to generate the serial bit-rate clock (SSPSCLK). The external clock is internally divided
by 2 and then further divided by the value in SSCR0[SCR].
If SSP operation is disabled, the five SSP pins are available for GPIO use. See Chapter 4, “System
Integration Unit” for details on configuring pin direction and interrupt capabilities.
8.3 Functional Description
Serial data is transferred between the processor and an external peripheral through FIFO buffers in
the SSPC. Data transfers to system memory are handled by either the CPU (using programmed I/O)
or by DMA. Operation is full duplex - separate buffers and serial data paths permit simultaneous
transfers to and from the external peripheral.
Programmed I/O transmits and receives data directly between the CPU and the transmit/receive
FIFO’s. The DMA controller transfers data during transmit and receive operations between
memory and the FIFO’s. DMA programming guidelines are found in Chapter 5, “DMA
Controller” .
8.3.1 Data Transfer
Transmit data is written by the CPU or DMA to the SSPC’s transmit FIFO. The write takes the
form of a programmed I/O or a DMA burst, with 4 or 8 half-words being transferred per burst. The
SSPC then takes the data from the FIFO, serializes it, and transmits it via the SSPTXD signal to the
peripheral. Data from the peripheral is received via the SSPRXD signal, converted to parallel
words and is stored in the Receive FIFO. Read operations automatically target the receive FIFO,
while write operations write data to the transmit FIFO. Both the transmit and receive FIFO buffers
are 16 entries deep by 16 bits wide.
As the received data fills the receive FIFO, a programmable threshold triggers an interrupt to the
Interrupt Controller. If enabled, an interrupt service routine responds by identifying the source of
the interrupt and then performs one or several read operations from the inbound (receive) FIFO
buffer.
8.4 Data Formats
The SSPC uses serial data formats to transfer and store data. This section describes the data
formats.
8.4.1 Serial Data Formats for Transfer to/from Peripherals
Four signals are used to transfer data between the processor and external codecs or modems.
Although there are three formats for serial data, they have the same basic structure:
• SSPSCLK–Defines the bit rate at which serial data is transmitted and received from the port.
• SSPSFRM–Depending on the transmission format selected, defines the boundaries of a data
frame, or marks the beginning of a data frame.
• SSPTXD–Transmit signal for outbound data, from system to peripheral.