Intel PXA255 - Manual (Page 433)

Intel® PXA255 Processor Developer’s Manual 12-31
USB Device Controller
12.6.5.7 Receive FIFO Not Empty (RNE)
The receive FIFO not empty bit indicates that unread data remains in the receive FIFO. This bit
must be polled when the UDCCSx[RPC] bit is set to determine if there is any data in the FIFO that
the DMA did not read. The receive FIFO must continue to be read until this bit clears or data will
be lost.
12.6.5.8 Receive Short Packet (RSP)
The UDC uses the receive short packet bit to indicate that the received OUT packet in the active
buffer currently being read is a short packet or zero-sized packet. This bit is updated by the UDC
after the last byte is read from the active buffer and reflects the status of the new active buffer. If
UDCCSx[RSP] is a one and UDCCSx[RNE] is a 0, it indicates a zero-length packet. If a zero-
length packet is present, the core must not read the data register. UDCCSx[RSP] is cleared when
the next OUT packet is received.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
12.6.6 UDC Endpoint x Control/Status Register (UDCCS3/8/13)
USCCS3/8/13, shown in Table 12-17 , contains 4 bits that are used to operate endpoint(x), an
Isochronous IN endpoint.
Table 12-17. UDCCS3/8/13 Bit Definitions
0x4060_001C
0x4060_0030
0x4060_0044
UDCCS3
UDCCS8
UDCC13
USB Device Controller
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
TS
P reserved
TU
R
FT
F
TPC TFS
Reset X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 1
Bit Name Description
31:8 — reserved
7 TSP
Transmit short packet (read/write 1 to set).
1 = Short packet ready for transmission.
6:4 — reserved
3 TUR
Transmit FIFO underrun (read/write 1 to clear)
1 = Transmit FIFO experienced an underrun.
2 FTF
Flush Tx FIFO (always read 0/ write a 1 to set)
1 = 1 – Flush Contents of TX FIFO
1 TPC
Transmit packet complete (read/write 1 to clear).
0 = Error/status bits invalid.
1 = Transmit packet has been sent and error/status bits are valid.
0 TFS
Transmit FIFO service (read-only).
0 = Transmit FIFO has no room for new data
1 = Transmit FIFO has room for at least 1 complete data packet