Intel PXA255 - Manual (Page 577)

Intel® PXA255 Processor Developer’s Manual 17-5
Hardware UART
17.4.2.1 FIFO Interrupt Mode Operation
17.4.2.1.1 Receive Interrupt
For a receive interrupt to occur, the receive FIFO and receive interrupts must be enabled. The
Interrupt Identification register (IIR) bits 1 and 2 (IIR[IID]) change to show that receive data is
available when the FIFO reaches its trigger threshold. IIR[IID] changes to show the next waiting
interrupt when the FIFO drops below the trigger threshold. A change in IIR[IID] triggers an
interrupt to the core. Software reads IIR[IID] to determine the cause of the interrupt.
The receiver line status interrupt (IIR = 0xC6) has the highest priority and the received data
available interrupt (IIR = 0xC4) is lower. The line status interrupt occurs only when the character at
the front of the FIFO has errors.
The data ready bit (DR in the Line Status register) is set when a character is transferred from the
shift register to the receive FIFO. The DR bit is cleared when the FIFO is empty.
17.4.2.1.2 Character Timeout Interrupt
A character timeout interrupt occurs when the receive FIFO and receive timeout interrupt are
enabled and these conditions exist:
• At least one character is in the FIFO.
• The most recently received character was received more than four continuous character times
ago. If two stop bits are programmed, the second is included in this interval.
• The most recent FIFO read was performed more than four continuous character times ago.
After the processor reads one character from the receive FIFO or a new start bit is received, the
timeout interrupt is cleared and the timeout is reset. If a timeout interrupt has not occurred, the
timeout is reset when a new character is received or the processor reads the receive FIFO.
17.4.2.1.3 Transmit Interrupt
Transmit interrupts can only occur when the transmit FIFO and transmit interrupt are enabled. The
transmit data request interrupt occurs when the transmit FIFO is at least half empty. The interrupt is
cleared when the Transmit Holding register (THR) is written or the IIR is read.
17.4.2.2 FIFO Polled Mode Operation
When the FIFOs are enabled, clearing both IER[DMAE] and IER[4:0] places the serial port in
FIFO polled operating mode. The receiver and the transmitter are controlled separately. Either one
or both can be in polled mode. In polled mode, software checks receiver and transmitter status via
the Line Status register (LSR). The processor polls the following bits for receive and transmit data
service:
• Receive Data Service – The processor checks the data ready (LSR[DR]) bit which is set when
one or more bytes remain in the receive FIFO or Receive Buffer register (RBR).
• Transmit Data Service – The processor checks the transmit data request (LSR[TDRQ]) bit
which is set when transmitter needs data.
The processor can also check the transmitter empty (LSR[TEMT]) bit, which is set when the
transmit FIFO and Transmit Holding register are empty.