Intel PXA255 - Manual (Page 74)

3-12 Intel® PXA255 Processor Developer’s Manual
Clocks and Power Manager
1. Configure the Memory Controller to ensure SDRAM contents are maintained during the
Frequency Change Sequence. The Memory Controller’s refresh timer must be programmed to
match the maximum refresh time associated with the slower of two frequencies (current and
desired). The SDRAM divide by two must be set to a value that prevents the SDRAM
frequency from exceeding the specified frequency. For example, to change from 100/100 to
133/66, the SDRAM bus must be set to divide by two before the frequency change. To change
from 133/66 to 100/100, the SDRAM must be set to one-to-one after the frequency change
sequence is completed. See
Section 6, “Memory Controller” for more details.
2. Disable the LCD Controller or configure it to avoid the effects of an interruption in the LCD
clocks and data from the processor.
3. Configure peripheral units to handle a lack of DMA service for up to 500 µs. If a peripheral
unit can not function for 500 µs without DMA service, it must be disabled.
4. Disable peripheral units that can not accommodate a 500 µs interrupt latency. The interrupts
generated during the Frequency Change Sequence are serviced when the sequence exits.
5. Program the CCCR ( Section 3.6.1, “Core Clock Configuration Register (CCCR)” ) to reflect
the desired frequency.
3.4.7.2 Invoking the Frequency Change Sequence
To invoke the Frequency Change Sequence, software must set FCS in the CCLKCFG (See
Section 3.7.1 ). When software sets FCS, it may also set or clear other bits in CCLKCFG. If
software sets the TURBO bit in the same write, the CPU enters Turbo Mode when the Frequency
Change Sequence exits.
After software sets the FCS:
1. The CPU clock stops and interrupts to the CPU are gated.
2. The Memory Controller completes all outstanding transactions in its buffers and from the
CPU. New transactions from the LCD or DMA controllers are ignored.
3. The Memory Controller places the SDRAM in self-refresh mode.
Note: Program the Memory Controller to ensure the correct self-refresh time for SDRAM, given the
slower of the current and desired clock frequencies.
3.4.7.3 Behavior During the Frequency Change Sequence
In the frequency change sequence, the processor’s PLL clock generator is in the process of locking
to the correct frequency and cannot be used. This means that interrupts cannot be processed.
Interrupts that occur during the frequency change sequence are serviced after the processor’s PLL
has locked. The 95.85 MHz and 147.46 MHz PLL clock generators are active and peripherals,
except the memory, LCD, and DMA controllers, may continue to operate normally, provided they
can accommodate the inability to process DMA or interrupt requests. DMA or interrupt requests
are not recognized until the frequency change sequence is complete.
The Imprecise Data Abort is also not recognized and if nVDD_FAULT or nBATT_FAULT is
asserted, the assertion is ignored until the Frequency Change Sequence exits. This means that the
processor does not enter Sleep Mode until the Frequency Change Sequence is complete.