Samsung MUXONENAND A-DIE KFM2G16Q2A - Manual (Page 76)

MuxOneNAND2G(KFM2G16Q2A-DEBx)
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FLASH MEMORY
MuxOneNAND4G(KFN4G16Q2A-DEBx)
Write Interrupt (WI)
This is the Write interrupt bit.
WI Interrupt [6]
Erase Interrupt (EI)
This is the Erase interrupt bit.
EI Interrupt [5]
Reset Interrupt (RSTI)
This is the Reset interrupt bit.
RSTI Interrupt [4]
Status Conditions
Default State Valid
State Interrupt
Function Cold Warm/hot
0 0 0 off
sets itself to ‘1’
At the completion of an Program Operation
(0080h, 001Ah, 001Bh, 007Dh, 007Fh)
0 → 1 Pending
clears to ‘0’
’0’ is written to this bit,
Cold/Warm/Hot reset is being performed, or com-
mand is written to Command Register in INT auto
mode
1 → 0 off
Status Conditions
Default State Valid
State Interrupt
Function
Cold Warm/hot
0 0 0 off
sets itself to ‘1’
At the completion of an Erase Operation
(0094h, 0095h, 0030h)
0 → 1 Pending
clears to ‘0’
’0’ is written to this bit,
Cold/Warm/Hot reset is being performed, or com-
mand is written to Command Register in INT auto
mode
1 → 0 off
Status Conditions
Default State Valid
State Interrupt
Function Cold Warm/hot
0 1 0 off
sets itself to ‘1’
At the completion of an Reset Operation
(00B0h, 00F0h, 00F3h or
warm reset is released)
0 → 1 Pending
clears to ‘0’
’0’ is written to this bit, or
command is written to Command Register in INT
auto mode
1 → 0 off