Samsung MUXONENAND A-DIE KFM2G16Q2A - Manual (Page 143)

MuxOneNAND2G(KFM2G16Q2A-DEBx)
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MuxOneNAND4G(KFN4G16Q2A-DEBx)
5.5 AC Characteristics for Asynchronous Read
See Timing Diagrams 6.5, 6.6, 6.22 and 6.23.
NOTE :
1) If OE is disabled at the same time or before CE is disabled, the output will go to high-z by t
OEZ .
If CE is disabled at the same time or before OE is disabled, the output will go to high-z by t CEZ .
If CE and OE are disabled at the same time, the output will go to high-z by t OEZ .
These parameters are not 100% tested.
2) This Parameter is valid at toggle bit timing in asynchronous read only. (timing diagram 6.21 and 6.22)
5.6 AC Characteristics for Warm Reset (RP), Hot Reset and NAND Flash Core Reset
See Timing Diagrams 6.18, 6.19 and 6.20
NOTE :
1) These parameters are tested based on INT bit of interrupt register. Because the time on INT pin is related to the pull-up and pull-down resistor value.
2) The device may reset if tRP < tRP min(200ns), but this is not guaranteed.
Parameter Symbol
KFM2G16Q2A/
KFN4G16Q2A Unit
Min Max
Access Time from CE Low tCE - 76 ns
Asynchronous Access Time from AVD Low tAA - 76 ns
Asynchronous Access Time from address valid tACC - 76 ns
Read Cycle Time tRC 76 - ns
AVD Low Time tAVDP 12 - ns
Address Setup to rising edge of AVD tAAVDS 5 - ns
Address Hold from rising edge of AVD tAAVDH 6 - ns
Output Enable to Output Valid tOE - 20 ns
CE Setup to AVD falling edge tCA 0 - ns
CE Disable to Output & RDY High Z 1) tCEZ - 20 ns
OE Disable to Output High Z 1) tOEZ - 15 ns
AVD High to OE Low tAVDO 0 - ns
CE Low to RDY Valid tCER - 15 ns
WE Disable to AVD Enable tWEA 15 - ns
Address to OE low tASO 2) 10 - ns
Parameter Symbol Min Max Unit
RP & Reset Command Latch to BootRAM Access
tReady1
(BootRAM)
- 5 µs
RP & Reset Command Latch(During Load Routines) to INT High (Note1)
tReady2
(NAND Flash
- 10 µs
RP & Reset Command Latch(During Program Routines) to INT High (Note1)
tReady2
(NAND Flash
- 20 µs
RP & Reset Command Latch(During Erase Routines) to INT High (Note1)
tReady2
(NAND Flash
- 500 µs
RP & Reset Command Latch(NOT During Internal Routines) to INT High (Note1)
tReady2
(NAND Flash
- 10 µs
RP Pulse Width (Note2) tRP 200 - ns