15 2x interleave cache program operation timing – Samsung MUXONENAND A-DIE KFM2G16Q2A User Manual

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6.15 2X Interleave Cache Program Operation Timing

1st dat

a i

npu

t

2nd dat

a i

nput

Add

ress Set

ting

2X cach

e

p

rog

ram Command

AD

Q

0

~

A1,

A

2

,

A

3

:

Addr

ess of

Da

ta

RAM to

b

e

wr

itt

en.

INT

:

Indicat

o

r f

o

r Dat

a

RA

M’

s

S

ta

tus (Read

y=Hig

h, Bu

sy=Lo

w

)

Ongo

ing S

tat

us : In

dicat

ed by

O

n

Go

bi

t in

Cont

roll

er S

tat

us

Reg

ister

[

15]

(F240h

)

4KB da

ta

inpu

t : Asynch W

rit

e / Synch W

rit

e availa

ble.

Command

inp

u

t an

d I

N

T b

it

or

pi

n b

ehavior

is

based

on

‘I

NT a

u

to

mod

e

’.

NOTE

:

1) INT pin might

to

ggle when

I

N

T

bi

t of

chip

1 tur

n

s

to

read

y be

for

e

h

o

st issues

‘2

X prog

ram’ command on

chip

2.

AD

Q

1

5

A1

A2

Hi

gh

-Z

INT

bi

t

.

...

.

.

4KB dat

a

in

to

2 Da

ta

RAMs

4KB

da

ta

in

to

2 Da

ta

RAMs

2

X

Cac

he

pr

ogr

am Command

2X pr

ogr

am

Command

Last dat

a i

npu

t

An

4

KB d

a

ta

in

to

2 Dat

a

RAM

s

.

..

Ongo

in

g

St

a

tu

s

C

o

nt

rol

le

r S

tat

us Reg

ist

er

Ch

eck

Pla

ne1 / Pl

ane

2

cu

rr

ent

: I

n

val

id

Pla

ne1 / Pl

ane

2

p

rev

io

us:

Pa

ss=

0, Fai

l=

1

Cont

ro

ller

S

ta

tu

s Re

gi

ste

r

Chec

k

Pla

ne1 /

Pl

an

e2 cur

ren

t :

Pas

s=0

, Fai

l=

1

Pl

ane1

/

Plan

e2 pr

evi

ous

: Pass

=0,

F

a

il=1

.

..

1s

t dat

a

input

2nd dat

a i

nput

Ad

dre

ss Set

tin

g

2X ca

che pr

ogr

am

Co

m

m

an

d

ADQ0~

ADQ15

A1

A2

.

..

.

.

4KB data

in

to

2 Dat

a

RAMs

4

KB d

a

ta

in

to

2

Dat

a

RAM

s

2X Cac

he pro

g

ra

m

Command

2X

pr

o

g

ra

m

C

o

m

m

an

d

Last

dat

a input

An

4

KB d

a

ta

in

to

2 D

a

ta

RAMs

.

..

O

n

go

ing

St

a

tu

s

Co

ntr

o

lle

r S

tat

us Regi

st

er

Ch

eck

Pl

an

e1 / Pl

ane2

c

u

rr

ent

: In

val

id

Pl

an

e1

/

Pl

ane2

p

rev

io

us:

Pa

ss=0

,

Fai

l=

1

Cont

ro

ller

S

tatu

s

R

e

gi

st

er

Chec

k

Pl

ane1

/

Pla

ne2 cur

re

n

t

:

Pa

ss=

0, Fai

l=

1

Pl

ane1

/

Pla

ne2 pr

evi

ous

: Pass

=0,

F

a

il=

1

.

..

Chip

1

Ch

ip

2

.

..

..

.

..

..

.

..

..

Cont

ro

ller

S

ta

tu

s Re

gi

ste

r

Chec

k

Pl

ane1

/

P

lan

e2 cur

re

n

t :

I

n

va

lid (F

ixe

d

to 0)

Pl

ane1

/

P

lan

e2 pr

evi

ous

: In

val

id

(

F

ix

ed t

o

0)

Cont

rol

le

r S

tat

us

Reg

is

ter

C

h

eck

Pla

ne1 /

Pl

ane

2 cur

ren

t : I

n

val

id

(Fi

xed

t

o

0)

Pla

ne1 /

Pl

ane

2 pre

vio

us:

Inv

a

lid (

F

ix

ed to

0)

IN

T bi

t

INT

P

in

.

..

1)

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