0 technical and application notes, 1 methods of determining interrupt status – Samsung MUXONENAND A-DIE KFM2G16Q2A User Manual

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MuxOneNAND2G(KFM2G16Q2A-DEBx)

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FLASH MEMORY

MuxOneNAND4G(KFN4G16Q2A-DEBx)

7.0 TECHNICAL AND APPLICATION NOTES

From time-to-time supplemental technical information and application notes pertaining to the design and operation of the device in a system
are included in this section. Contact your Samsung Representative to determine if additional notes are available.

7.1 Methods of Determining Interrupt Status

There are two methods of determining Interrupt Status on the MuxOneNAND. Using the INT pin or monitoring the Interrupt Status Register Bit.

The MuxOneNAND INT pin is an output pin function used to notify the Host when a command has been completed. In ‘Cache Read’, ‘Syn-
chronous Burst Block Read’ and ‘2X Cache Program’ cases, INT pin notifies that only trasferring from DataRAM to page buffer is completed.
This provides a hardware method of signaling the completion of a program, erase, or load operation.

In its normal state, the INT pin is high if the INT polarity bit is default. In case of normal INT mode, before a command is written to the com-
mand register, the INT bit must be written to '0' for the INT pin transitions to a low state indicating start of the operation. In case of ‘INT auto
mode’, INT bit is written to ‘0’ automatically right after command issued. Upon completion of the command operation by the MuxOneNAND’s
internal controller, INT returns to a high state.

INT pin is a DQ-type output except ‘Reset’ and ‘2X program’ in DDP allowing two INT outputs to be Or-tied together. In case of ‘Reset’ and ‘2X
Program’ in DDP, INT pin operates as an open drain with 50K ohm. INT pin does not float to a hi-Z condition when CE is disabled or OE is dis-
abled. Refer to section 2.8 for additional information about INT.

INT can be implemented by tying INT to a host GPIO or by continuous polling of the Interrupt status register.

INT Type (Mono)

INT Type (DDP)

General Operation

DQ type

DQ type

Reset Operation (Cold,Warm,Hot and Flash Core Reset) and 2X Program

DQ type

Open drain

(with 50K ohm)

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