Samsung MUXONENAND A-DIE KFM2G16Q2A - Manual (Page 75)

MuxOneNAND2G(KFM2G16Q2A-DEBx)
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FLASH MEMORY
MuxOneNAND4G(KFN4G16Q2A-DEBx)
2.8.22 Interrupt Status Register F241h (R/W)
This Read/Write register shows status of the MuxOneNAND interrupts.
In DDP, INT register will not be written if DBS, DFS is not set.
F241h, defaults = 8080h after Cold Reset; 8010h after Warm/Hot Reset
Interrupt (INT)
This is the master interrupt bit. The INT bit is wired directly to the INT pin on the chip. Upon writing '0' to the INT bit, the INT pin goes low if
INTpol is high and goes high if INTpol is low.
INT Interrupt [15]
Read Interrupt (RI)
This is the Read interrupt bit.
RI Interrupt [7]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT Reserved(0000000) RI WI EI RSTI Reserved(0000)
Status Conditions
Default State Valid
State
Interrupt
Function Cold Warm/hot
1 1 0 off
sets itself to ‘1’
One or more of RI, WI, RSTI and EI is set to ‘1’, or
0065h, 0023h, 0071h, 002Ah, 0027h and 002Ch
commands are completed.
0 → 1 Pending
clears to ‘0’
’0’ is written to this bit,
Cold/Warm/Hot reset is being performed, or
command is written to Command Register in INT
auto mode
1 → 0 off
Status Conditions
Default State Valid
State Interrupt
Function Cold Warm/hot
1 0 0 off
sets itself to ‘1’
At the completion of an Load Operation
(0000h, 000Eh, 000Ch, 000Ah, 0013h,
Load Data into Buffer, or boot is done)
0 → 1 Pending
clears to ‘0’
’0’ is written to this bit,
Cold/Warm/Hot reset is being performed, or
command is written to Command Register in INT
auto mode
1 → 0 off