Flex-muxonenand4g(kfm4gh6q4m-debx) – Samsung FLEX-MUXONENAND KFN8GH6Q4M User Manual
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Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
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FLASH MEMORY
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)
3.6.2 LSB Page Recovery Read
MLC NAND Flash cell has paired pages - LSB page and MSB page. LSB page has lower page address and MSB page has higher page
address in paired pages. If power off occurs during MSB page program, the paired LSB page data can become corrupt. LSB page recovery
read is a way to read LSB page though page data are corrupted. When uncorrectable error occurrs as a result of LSB page read after power
up, issue LSB page recovery read. Its command is ‘0005h’. Flow chart below shows LSB page read sequence.
LSB Page Recovery read flow chart
NOTE :
1) BSA must be 1000.
2) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
Write ‘DFS, FBA’ of Flash
Add: F100h DQ=DFS*, FBA
Start
Write ‘FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Write ‘Load’ Command
Add=F220h DQ=0000h
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
NO
Select DataRAM for DDP
Add: F101h DQ=DBS*
Write 0 to INT register
2)
Add: F241h DQ=0000h
Write ‘BSA
1)
, BSC’ of DataRAM
Add: F200h DQ=0800h
Write System Configuration
Add: F221h DQ=ECC
Register
Read ECC Status Register1
Add: FF00h DQ=ER1[12:8],
Read ECC Status Register2
Add: FF01h DQ=ER3[12:8],
Read ECC Status Register3
Add: FF02h DQ=ER5[12:8],
Read ECC Status Register4
Add: FF03h DQ=ER7[12:8],
Read Controller status register
Add: F240h DQ[10]=Error
Read Completed
Host reads data from
DataRAM
DQ[10]=0?
YES
Write ‘DFS, FBA’ of Flash
Add: F100h DQ=DFS*, FBA
Write ‘FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Write ‘LSB Page Recovery Read’
Add=F220h DQ=0005h
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
Select DataRAM for DDP
Add: F101h DQ=DBS*
Write 0 to INT register
Add: F241h DQ=0000h
Write ‘BSA
,
BSC’ of DataRAM
Add: F200h DQ=0800h
Write System Configuration
Add: F221h DQ=ECC
Register
Command
ER0[4:0]
ER2[4:0]
ER4[4:0]
ER6[4:0]
* DBS, DFS is for DDP
Read ECC Status Register1
Add: FF00h DQ=ER1[12:8],
Read ECC Status Register2
Add: FF01h DQ=ER3[12:8],
Read ECC Status Register3
Add: FF02h DQ=ER5[12:8],
Read ECC Status Register4
Add: FF03h DQ=ER7[12:8],
Read Completed
Host reads data from
DataRAM
ER0[4:0]
ER2[4:0]
ER4[4:0]
ER6[4:0]
Load Error
DQ[10]=0?
NO
YES
Read Controller status register
Add: F240h DQ[10]=Error