Samsung FLEX-MUXONENAND KFN8GH6Q4M - Manual (Page 76)

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
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FLASH MEMORY
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)
Program Interleave(@DDP) Flow Chart
NOTE :
1) DBS must be set before data input.
2) FSA must be 00 and BSC must be 000 within program operation
3) BSA must be 1000 and BSC must be 000.
Start
Write ‘DFS*, FBA’ of Flash
Add: F100h DQ=DFS*, FBA
Write ‘FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA 2)
Select DataRAM for DDP 1)
Add: F101h DQ=DBS*
Write Data into DataRAM
Add: DataRAM, DQ=Data(4KB)
Write ‘BSA, BSC’ of DataRAM
Add: F200h DQ=0800 3)
Read Write Protection Status
Add: F24Eh DQ=US,LS,LTS
Write Program command
Add: F220h DQ=0080h
Check for INT register high
Add: F241h DQ[15]=INT
Select DataRAM for DDP 1)
Add: F101h DQ=DBS*
INT=1(Ready)
{
1
*
Write ‘DFS*, FBA’ of Flash
Add: F100h DQ=DFS*, FBA
Write ‘FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA 2)
Select DataRAM for DDP 1)
Add: F101h DQ=DBS*
Write Data into DataRAM
Add: DataRAM, DQ=Data(4KB)
Write ‘BSA, BSC’ of DataRAM
Add: F200h DQ=0800 3)
Read Write Protection Status
Add: F24Eh DQ=US,LS,LTS
Write Program command
Add: F220h DQ=0080h
Wait for INT register
low to high transition
Add: F241h DQ[6]=WI
Select DataRAM for DDP 1)
Add: F101h DQ=DBS*
Read Controller status register
Add: F240h DQ[10]=Error
NO(Program Fail)
DQ[10]=0?
{
2
*
YES(Program Pass)
Program Error
Has Final Program
command been issued?
YES
(Final Program status check)
Select DataRAM for DDP 1)
Add: F101h DQ=DBS*
Wait for INT register
low to high transition
Add: F241h DQ[6]=WI
Read Controller status register
Add: F240h DQ[10]=Error
YES(Program Pass)
DQ[10]=0?
Program completed
Program Error
NO(Program Fail)
}
3
*
* DBS, DFS is for DDP
Previous Program Status Check
DBS must be changed to indicate chip. Program has been issued prior to current program ongoing
2
*
1
*
Check the chip status before command issues.
* Program Interleave can work in Auto INT
Mode.
Interrupt register must not be written.
Final Program Status Check 3
*
NO