Lakeshore Learning Materials 642 - Manual (Page 64)

Lake Shore Model 642 Electromagnet Power Supply User’s Manual
5-12 Computer Interface Operation
5.1.4.4 Status Byte and Service Request (SRQ)
As shown in Figure 5-1, the Status Byte Register receives the summary bits from the two status register sets and the
message available summary bit from the output buffer. The status byte is used to generate a service request (SRQ). The
selection of summary bits that will generate an SRQ is controlled by the Service Request Enable Register.
5.1.4.4.1 Status Byte Register
The summary messages from the event registers and output buffer set or clear the summary bits of the Status Byte
Register, see Figure 5-5. These summary bits are not latched. Clearing an event register will clear the corresponding
summary bit in the Status Byte Register. Reading all messages in the output buffer, including any pending queries, will
clear the message available bit. The bits of the Status Byte Register are described as follows:
Operation Summary (OSB), Bit (7) – Set summary bit indicates that an enabled operation event has occurred.
Request Service (RQS)/Master Summary Status (MSS), Bit (6) – This bit is set when a summary bit and the summary
bits corresponding enable bit in the Service Request Enable Register are set. Once set, the user may read and clear the
bit in two different ways, which is why it is referred to as both the RQS and the MSS bit. When this bit goes from low
to high, the Service Request hardware line on the bus is set, this is the RQS function of the bit. See Paragraph
5.1.4.4.3. In addition, the status of the bit may be read with the *STB? query which returns the binary weighted sum of
all bits in the Status Byte, this is the MSS function of the bit.
Performing a serial poll will automatically clear the RQS function but not the MSS function. A *STB? will read the
status of the MSS bit (along with all of the summary bits), but also will not clear it. To clear the MSS bit, either clear
the event register that set the summary bit or disable the summary bit in the Service Request Enable Register.
Event Summary (ESB), Bit (5) – Set summary bit indicates that an enabled standard event has occurred.
Message Available (MAV), Bit (4) – Set summary bit indicates that a message is available in the output buffer.
Bit (3) – Not used.
Hardware Errors Summary (HESB), Bit (2) – Set summary bit indicates that an enabled hardware error event has
occurred.
Operational Errors Summary (OESB), Bit (1) – Set summary bit indicates that an enabled operational error event has
occurred.
AND
AND OR
MSS
*SRE, *SRE?
Read by *STB?
Enable Register
Service Request
OSB
7
Not
Used
6
ESB
5 3
Not
Used
MAV
4 2
Name
0
Not
Used
1 Bit
RQS
AND
7 Status Byte
request. Reset by
Generate service
serial poll.
*STB?
Register
OSB
2 3 5 6 4
MSS RQS ESB
Used
Not MAV
Bit 0 1
Name
Used
Not
From Operation Condition Register
From Standard Event Status Register
From Output Buffer
From Error Status Register (Hardware)
From Error Status Register (Operational)
Figure 5-6. Status Byte Register and Service Request Enable Register