Pepper Computer Modular Computers RS485 - Manual (Page 66)

SMART I/O User’s Manual
March 12, 1996 ©1996 PEP Modular Computers GmbH Page 2 - 26
Chapter 2 SMART-BASE
2.6.8 SMTstat
Syntax
error_code SMTstat(u_int8 *value);
Description
This function reads the timer status register and clears it if set.
Input
u_int8 *value
Pointer to a variable in which to place the read
value. 0 represents not set, 1 represents set
Output
error_code SUCCESS
or standard OS-9 error code (refer to the OS-9
Technical Manual Error Codes Section).
Example
RetVal = SMTstat(buffer);
Description of the Timer Status Register (TSR)
The timer status register contains one bit from which the zero detect status
can be determined. The ZDS status bit (bit 0) is an edge-sensitive flip-flop
that is set to one when the 24-bit counter decrements from $000001 to
$000000. The ZDS status bit is cleared to zero following the direct reset
operation or when the timer is halted. This register is always readable
without consequence. A write access performs a direct reset operation if bit
0 in the written data is one!
7 6 5 4 3 2 1 0
• • • • • • • ZDS