Texas Instruments TMS320F2802 User Manual
Page 113
t
w(WAKE-INT)
t
d(WAKE-STBY)
t
d(IDLE−XCOL)
Wake−up
Signal
X1/X2 or
X1 or
XCLKIN
XCLKOUT
STANDBY
Normal Execution
STANDBY
Flushing Pipeline
(A)
(B)
(C)
(D)
(E)
(F)
Device
Status
,
,
,
SPRS230N – OCTOBER 2003 – REVISED MAY 2012
Table 6-18. STANDBY Mode Timing Requirements
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Without input qualification
3t
c(OSCCLK)
Pulse duration, external
t
w(WAKE-INT)
cycles
wake-up signal
With input qualification
(1)
(2 + QUALSTDBY) * t
c(OSCCLK)
(1)
QUALSTDBY is a 6-bit field in the LPMCR0 register.
Table 6-19. STANDBY Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay time, IDLE instruction
t
d(IDLE-XCOL)
32t
c(SCO)
45t
c(SCO)
cycles
executed to XCLKOUT low
Delay time, external wake signal
to program execution resume
(1)
Without input qualifier
100t
c(SCO)
•
Wake up from flash
cycles
–
Flash module in active
With input qualifier
100t
c(SCO)
+ t
w(WAKE-INT)
state
t
d(WAKE-STBY)
Without input qualifier
1125t
c(SCO)
•
Wake up from flash
cycles
–
Flash module in sleep
With input qualifier
1125t
c(SCO)
+ t
w(WAKE-INT)
state
Without input qualifier
100t
c(SCO)
cycles
•
Wake up from SARAM
With input qualifier
100t
c(SCO)
+ t
w(WAKE-INT)
(1)
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
A.
IDLE instruction is executed to put the device into STANDBY mode.
B.
The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles (if CLKINDIV = 0)
or 64 cycles (if CLKINDIV = 1) before being turned off. This delay enables the CPU pipe and any other pending
operations to flush properly.
C.
Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode.
D.
The external wake-up signal is driven active.
E.
After a latency period, the STANDBY mode is exited.
F.
Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 6-15. STANDBY Entry and Exit Timing Diagram
Copyright © 2003–2012, Texas Instruments Incorporated
Electrical Specifications
113
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