Texas Instruments TMS320DM357 - Manual (Page 24)

2.4 USB PHY Initialization
2.5 Dynamic FIFO Sizing
3 USB Controller Host and Peripheral Modes Operation
USB Controller Host and Peripheral Modes Operation www.ti.com
The following bits in USBPHY_CTL must be cleared to enable the USB controller: OSCPDWN and
PHYPDWN. The following bits in USBPHY_CTL must be set to enable the level comparators: VBDTCTEN
and VBUSENS. After this configuration is in place, wait until the PLL clock is good prior to continuing, i.e.,
wait until USBPHY_CTL.PHYCLKGD bit is set.
The USB controller supports a total of 4K RAM to dynamically allocate FIFO to all endpoints. The
allocation of FIFO space to the different endpoints requires the specification for each Tx and Rx endpoint
of:
•
The start address of the FIFO within the RAM block
•
The maximum size of packet to be supported
•
Whether double-buffering is required.
These details are specified through four registers, which are added to the indexed area of the memory
map. That is, the registers for the desired endpoint are accessed after programming the INDEX register
with the desired endpoint value.
Section 4.79 , Section 4.80 , Section 4.81 , and Section 4.82 provide details
of these registers.
Note: The option of setting FIFO sizes dynamically only applies to Endpoints 1
…
4. Endpoint 0
FIFO has a fixed size (64 bytes) and a fixed location (start address 0).
It is the responsibility of the firmware to ensure that all the Tx and Rx endpoints that are
active in the current USB configuration have a block of RAM assigned exclusively to that
endpoint that is at least as large as the maximum packet size set for that endpoint.
The USB controller can be used in a range of different environments. It can be used as either a
high-speed or a full-speed USB peripheral device attached to a conventional USB host (such as a PC). It
can be used as either host or peripheral device in point-to-point data transfers with another peripheral
device - or, if the other device also contains a Dual-Role Controller, the two devices can switch roles as
required. (This second device may be either a high-speed, full-speed or low-speed USB function.) Or the
controller can be used as the host to a range of such peripheral devices in a multi-point setup.
Whether the controller expects to behave as a host or as a peripheral device depends on the way the
devices are cabled together. Each USB cable has an A end and a B end. If the A end of the cable is
plugged into the controller, it will take the role of the Host device and go into host mode. If the B end of
the cable is plugged in, the controller will go instead into peripheral mode.
The USB controller interrupts the ARM on completion of the data transfer on any of the endpoints or on
detecting reset, resume, suspend, connect, disconnect, or SOF on the bus.
When the ARM is interrupted with a USB interrupt, it needs to read the interrupt status register to
determine the endpoints that have caused the interrupt and jump to the appropriate routine. If multiple
endpoints have caused the interrupt, endpoint 0 should be serviced first, followed by the other endpoints.
The suspend interrupt should be serviced last.
The flowchart in Figure 2 describes the interrupt service routine for the USB module.
The following sections describe the programming of USB controller in Peripheral mode and Host mode.
DMA Operations and Interrupt Handler mechanisms are common to both peripheral and host mode
operations and are discussed after the programming in Peripheral and Host Mode.
24 Universal Serial Bus (USB) Controller SPRUGH3 – November 2008
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