Texas Instruments TMS320DM357 - Manual (Page 27)

3.1.1.1 Zero Data Requests
3.1.1.2 Write Requests
www.ti.com USB Controller Host and Peripheral Modes Operation
Note: The Setup packet associated with any standard device request should include an 8-byte
command. Any setup packet containing a command field of anything other than 8 bytes will
be automatically rejected by the controller.
Zero data requests have all their information included in the 8-byte command and require no additional
data to be transferred. Examples of Zero Data standard device requests are:
•
SET_FEATURE
•
CLEAR_FEATURE
•
SET_ADDRESS
•
SET_CONFIGURATION
•
SET_INTERFACE
The sequence of events will begin, as with all requests, when the software receives an endpoint 0
interrupt. The RXPKTRDY bit of PERI_CSR0 (bit 0) will also have been set. The 8-byte command should
then be read from the endpoint 0 FIFO, decoded and the appropriate action taken.
For example, if the command is SET_ADDRESS, the 7-bit address value contained in the command
should be written to the FADDR register. The PERI_CSR0 register should then be written to set the
SERV_RXPKTRDY bit (bit 6) (indicating that the command has been read from the FIFO) and to set the
DATAEND bit (bit 3) (indicating that no further data is expected for this request). The interval between
setting SERV_RXPKTRDY bit and DATAEND bit should be very small to avoid getting a SetupEnd error
condition.
When the host moves to the status stage of the request, a second endpoint 0 interrupt will be generated to
indicate that the request has completed. No further action is required from the software. The second
interrupt is just a confirmation that the request completed successfully. For SET_ADDRESS command,
the address should be set in FADDR register only after the status stage interrupt is received.
If the command is an unrecognized command, or for some other reason cannot be executed, then when it
has been decoded, the PERI_CSR0 register should be written to set the SERV_RXPKTRDY bit (bit 6) and
to set the SENDSTALL bit (bit 5). When the host moves to the status stage of the request, the controller
will send a STALL to tell the host that the request was not executed. A second endpoint 0 interrupt will be
generated and the SENTSTALL bit (bit 2 of PERI_CSR0) will be set.
If the host sends more data after the DATAEND bit has been set, then the controller will send a STALL.
An endpoint 0 interrupt will be generated and the SENTSTALL bit (bit 2 of PERI_CSR0) will be set.
Note: DMA is not supported for endpoint 0, so the command should be read by accessing the
endpoint 0 FIFO register.
Write requests involve an additional packet (or packets) of data being sent from the host after the 8-byte
command. An example of a Write standard device request is: SET_DESCRIPTOR.
The sequence of events will begin, as with all requests, when the software receives an endpoint 0
interrupt. The RXPKTRDY bit of PERI_CSR0 will also have been set. The 8-byte command should then
be read from the Endpoint 0 FIFO and decoded.
As with a zero data request, the PERI_CSR0 register should then be written to set the SERV_RXPKTRDY
bit (bit 6) (indicating that the command has been read from the FIFO) but in this case the DATAEND bit
(bit 3) should not be set (indicating that more data is expected).
When a second endpoint 0 interrupt is received, the PERI_CSR0 register should be read to check the
endpoint status. The RXPKTRDY bit of PERI_CSR0 should be set to indicate that a data packet has been
received. The COUNT0 register should then be read to determine the size of this data packet. The data
packet can then be read from the endpoint 0 FIFO.
SPRUGH3 – November 2008 Universal Serial Bus (USB) Controller 27
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