Texas Instruments TMS320DM357 - Manual (Page 54)

3.2.3 Host Mode: Interrupt Transactions
USB Controller Host and Peripheral Modes Operation www.ti.com
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The HOST_TXINTERVAL register needs to be written with the required value for the NAK limit (2 - 215
frames/microframes), or cleared to 0 if the NAK timeout feature is not required.
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The relevant interrupt enable bit in the INTRTXE register should be set (if an interrupt is required for
this endpoint).
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The following bits of HOST_TXCSR register should be set as shown below:
– Set the MODE bit (bit 13) to 1 to ensure the FIFO is enabled (only necessary if the FIFO is shared
with an Rx endpoint).
– Set the DMAEN bit (bit 12) to 1 if a DMA request is required for this endpoint.
– Clear the FRCDATATOG bit (bit 11) to 0 to allow normal data toggle operations.
– Set the DMAMODE bit (bit 10) to 1 when DMA is enabled and the endpoint interrupt is not needed
for each packet transmission.
When the endpoint is first configured, the endpoint data toggle should be cleared to 0 either by using the
DATATOGWREN bit and DATATOG bit of HOST_TXCSR (bit 9 and bit 8) to toggle the current setting or
by setting the CLRDATATOG bit of HOST_TXCSR (bit 6). This will ensure that the data toggle (which is
handled automatically by the controller) starts in the correct state. Also, if there are any data packets in
the FIFO (indicated by the FIFONOTEMPTY bit of HOST_TXCSR register (bit 1) being set), they should
be flushed by setting the FLUSHFIFO bit (bit 3 of HOST_TXCSR).
Note: It may be necessary to set this bit twice in succession if double buffering is enabled.
3.2.2.2.2 Operation
When Bulk data is required to be sent to the USB peripheral device, the software should write the first
packet of the data to the FIFO (or two packets if double-buffered) and set the TXPKTRDY bit in the
corresponding HOST_TXCSR register (bit 0). The controller will then send an OUT token to the selected
peripheral endpoint, followed by the first data packet from the FIFO.
If data is correctly received by the peripheral device, an ACK should be received whereupon the controller
will clear TXPKTRDY bit of HOST_TXCSR (bit 0). If the USB peripheral device responds with a STALL,
the RXSTALL bit (bit 5) of HOST_TXCSR is set. If a NAK is received, the controller tries again and
continues to try until either the transaction is successful or the NAK limit set in the HOST_TXINTERVAL
register is reached. If no response at all is received, two further attempts are made before the controller
reports an error by setting ERROR bit in HOST_TXCSR (bit 2).
The controller then generates the appropriate endpoint interrupt, whereupon the software should read the
corresponding HOST_TXCSR register to determine whether the RXSTALL (bit 5), ERROR (bit 2) or
NAK_TIMEOUT (bit 7) bit is set and act accordingly. If the NAK_TIMEOUT bit is set, the controller can be
directed either to continue trying this transaction (until it times out again) by clearing the NAK_TIMEOUT
bit or to abort the transaction by flushing the FIFO before clearing the NAK_TIMEOUT bit.
If large blocks of data are being transferred, then the overhead of calling an interrupt service routine to
load each packet can be avoided by using DMA.
3.2.2.2.3 Error Handling
If the target wants to shut down the Bulk OUT pipe, it will send a STALL response. This is indicated by the
RXSTALL bit of HOST_TXCSR register (bit 5) being set.
When the controller is operating as the host, interactions with an Interrupt endpoint on the USB peripheral
device are handled in very much the same way as the equivalent Bulk transactions (described in previous
sections).
The principal difference as far as operational steps are concerned is that PROT field of HOST_RXTYPE
and HOST_TXTYPE (bits 5:4) need to be set (binary value) to represent an Interrupt transaction.
The required polling interval also needs to be set in the HOST_RXINTERVAL and HOST_TXINTERVAL
registers.
Universal Serial Bus (USB) Controller 54 SPRUGH3 – November 2008
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