Texas Instruments TMS320DM357 - Manual (Page 44)

3.2 USB Controller Host Mode Operation
3.2.1 Host Mode: Control Transactions
USB Controller Host and Peripheral Modes Operation www.ti.com
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Entry into Suspend mode. When operating as a host, the controller can be prompted to enter Suspend
mode by setting the SUSPENDM bit in the POWER register. When this bit is set, the controller will
complete the current transaction then stop the transaction scheduler and frame counter. No further
transactions will be started and no SOF packets will be generated. If the ENSUSPM bit (bit 0 of
POWER register) is set, PHY will go into low-power mode when the controller enters Suspend mode.
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Sending Resume Signaling. When the application requires the controller to leave Suspend mode, it
must clear the SUSPENDM bit in the POWER register (bit 1), set the RESUME bit (bit 2) and leave it
set for 20ms. While the RESUME bit is high, the controller will generate Resume signaling on the bus.
After 20 ms, the application should clear the Resume bit, at which point the frame counter and
transaction scheduler will be started.
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Responding to Remote Wake-up. If Resume signaling is detected from the target while the controller is
in Suspend mode, the PHY will be brought out of low-power mode. The controller will then exit
Suspend mode and automatically set the RESUME bit in the POWER register (bit 2) to take over
generating the Resume signaling from the target. If the Resume interrupt is enabled, an interrupt will
be generated.
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Reset Signaling. If the RESET bit in the POWER register (bit 3) is set while the controller is in Host
mode, it will generate Reset signaling on the bus. If the HSENAB bit in the POWER register (bit 5) was
set, it will also try to negotiate for high-speed operation. The software should keep the RESET bit set
for at least 20 ms to ensure correct resetting of the target device. After the software has cleared the bit,
the controller will start its frame counter and transaction scheduler. Whether high-speed operation is
selected will be indicated by HSMODE bit of POWER register (bit 4).
Host Control Transactions are conducted through Endpoint 0 and the software is required to handle all the
Standard Device Requests that may be sent or received via Endpoint 0 (as described in Universal Serial
Bus Specification, Revision 2.0, Chapter 9).
As for a USB peripheral device, there are three categories of Standard Device Requests to be handled:
Zero Data Requests (in which all the information is included in the command), Write Requests (in which
the command will be followed by additional data), and Read Requests (in which the device is required to
send data back to the host).
1. Zero Data Requests consist of a SETUP command followed by an IN Status Phase
2. Write Requests consist of a SETUP command, followed by an OUT Data Phase which is in turn
followed by an IN Status Phase
3. Read Requests consist of a SETUP command, followed by an IN Data Phase which is in turn followed
by an OUT Status Phase
A timeout may be set to limit the length of time for which the controller will retry a transaction which is
continually NAKed by the target. This limit can be between 2 and 215 frames/ microframes and is set
through the HOST_NAKLIMIT0 register. The following sections describe the CPU actions required for
these different types of requests by examining the steps to take in the different Control Transaction
phases.
Universal Serial Bus (USB) Controller 44 SPRUGH3 – November 2008
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