Texas Instruments TMS320DM357 - Manual (Page 31)

3.1.1.5 Endpoint 0 Service Routine
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An Endpoint 0 interrupt is generated when:
•
The controller sets the RXPKTRDY bit of PERI_CSR0 (bit 0) after a valid token has been received and
data has been written to the FIFO.
•
The controller clears the TXPKTRDY bit of PERI_CSR0 (bit 1) after the packet of data in the FIFO has
been successfully transmitted to the host.
•
The controller sets the SENTSTALL bit of PERI_CSR0 (bit 2) after a control transaction is ended due
to a protocol violation.
•
The controller sets the SETUPEND bit of PERI_CSR0 (bit 4) because a control transfer has ended
before DATAEND (bit 3 of PERI_CSR0) is set.
Whenever the endpoint 0 service routine is entered, the software must first check to see if the current
control transfer has been ended due to either a STALL condition or a premature end of control transfer. If
the control transfer ends due to a STALL condition, the SENTSTALL bit would be set. If the control
transfer ends due to a premature end of control transfer, the SETUPEND bit would be set. In either case,
the software should abort processing the current control transfer and set the state to IDLE.
Once the software has determined that the interrupt was not generated by an illegal bus state, the next
action taken depends on the endpoint state.
Figure 5 shows the flow of this process.
If endpoint 0 is in IDLE state, the only valid reason an interrupt can be generated is as a result of the
controller receiving data from the bus. The service routine must check for this by testing the RXPKTRDY
bit of PERI_CSR0 (bit 0). If this bit is set, then the controller has received a SETUP packet. This must be
unloaded from the FIFO and decoded to determine the action the controller must take. Depending on the
command contained within the SETUP packet, endpoint 0 will enter one of three states:
•
If the command is a single packet transaction (SET_ADDRESS, SET_INTERFACE etc.) without any
data phase, the endpoint will remain in IDLE state.
•
If the command has an OUT data phase (SET_DESCRIPTOR etc.), the endpoint will enter RX state.
•
If the command has an IN data phase ( GET_DESCRIPTOR etc.), the endpoint will enter TX state.
If the endpoint 0 is in TX state, the interrupt indicates that the core has received an IN token and data
from the FIFO has been sent. The software must respond to this either by placing more data in the FIFO if
the host is still expecting more data or by setting the DATAEND bit to indicate that the data phase is
complete. Once the data phase of the transaction has been completed, endpoint 0 should be returned to
IDLE state to await the next control transaction.
Note: All command transactions include a field that indicates the amount of data the host expects
to receive or is going to send.
If the endpoint is in RX state, the interrupt indicates that a data packet has been received. The software
must respond by unloading the received data from the FIFO. The software must then determine whether it
has received all of the expected data. If it has, the software should set the DATAEND bit and return
endpoint 0 to IDLE state. If more data is expected, the firmware should set the SERV_RXPKTRDY bit of
PERI_CSR0 (bit 6) to indicate that it has read the data in the FIFO and leave the endpoint in RX state.
SPRUGH3 – November 2008 Universal Serial Bus (USB) Controller 31
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