Texas Instruments TMS320DM357 User Manual
Page 36
USB Controller Host and Peripheral Modes Operation
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3.1.1.5.4
Error Handling
A control transfer may be aborted due to a protocol error on the USB, the host prematurely ending the
transfer, or if the software wishes to abort the transfer (e.g., because it cannot process the command).
The controller automatically detects protocol errors and sends a STALL packet to the host under the
following conditions:
•
The host sends more data during the OUT Data phase of a write request than was specified in the
command. This condition is detected when the host sends an OUT token after the DATAEND bit (bit 3
of PERI_CSR0) has been set.
•
The host requests more data during the IN Data phase of a read request than was specified in the
command. This condition is detected when the host sends an IN token after the DATAEND bit in the
PERI_CSR0 register has been set.
•
The host sends more than Max Packet Size data bytes in an OUT data packet.
•
The host sends a non-zero length DATA1 packet during the STATUS phase of a read request.
When the controller has sent the STALL packet, it sets the SENTSTALL bit (bit 2 of PERI_CSR0) and
generates an interrupt. When the software receives an endpoint 0 interrupt with the SENTSTALL bit set, it
should abort the current transfer, clear the SENTSTALL bit, and return to the IDLE state.
If the host prematurely ends a transfer by entering the STATUS phase before all the data for the request
has been transferred, or by sending a new SETUP packet before completing the current transfer, then the
SETUPEND bit (bit 4 of PERI_CSR0) will be set and an endpoint 0 interrupt generated. When the
software receives an endpoint 0 interrupt with the SETUPEND bit set, it should abort the current transfer,
set the SERV_SETUPEND bit (bit 7 of PERI_CSR0), and return to the IDLE state. If the RXPKTRDY bit
(bit 0 of PERI_CSR0) is set this indicates that the host has sent another SETUP packet and the software
should then process this command.
If the software wants to abort the current transfer, because it cannot process the command or has some
other internal error, then it should set the SENDSTALL bit (bit 5 of PERI_CSR0). The controller will then
send a STALL packet to the host, set the SENTSTALL bit (bit 2 of PERI_CSR0) and generate an endpoint
0 interrupt.
3.1.1.5.5
Additional Conditions
When working as a peripheral device, the controller automatically responds to certain conditions on the
USB bus or actions by the host. The details are given below:
•
Stall Issued to Control Transfers
–
The host sends more data during an OUT Data phase of a Control transfer than was specified in
the device request during the SETUP phase. This condition is detected by the controller when the
host sends an OUT token (instead of an IN token) after the software has unloaded the last OUT
packet and set DataEnd.
–
The host requests more data during an IN data phase of a Control transfer than was specified in
the device request during the SETUP phase. This condition is detected by the controller when the
host sends an IN token (instead of an OUT token) after the software has cleared TXPKTRDY and
set DataEnd in response to the ACK issued by the host to what should have been the last packet.
–
The host sends more than MaxPktSize data with an OUT data token.
–
The host sends the wrong PID for the OUT Status phase of a Control transfer.
–
The host sends more than a zero length data packet for the OUT Status phase.
•
Zero Length Out Data Packets In Control Transfer
–
A zero length OUT data packet is used to indicate the end of a Control transfer. In normal
operation, such packets should only be received after the entire length of the device request has
been transferred (i.e., after the software has set DataEnd). If, however, the host sends a zero
length OUT data packet before the entire length of device request has been transferred, this signals
the premature end of the transfer. In this case, the controller will automatically flush any IN token
loaded by software ready for the Data phase from the FIFO and set SETUPEND bit (bit 4 of
PERI_CSR0).
Universal Serial Bus (USB) Controller
36
SPRUGH3 – November 2008