ARM IM-AD1 - Manual (Page 49)

Reference Design Example
ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 4-3
Figure 4-1 Design example architecture
Table 4-1 provides a summary description of the supplied VHDL files. A more detailed
description of each VHDL block is included within the files in the form of comments.
AHB
to
APB
bridge
UART
PIB
AHB
SSP
GPIO A
Stepper A
DC/DC
converter
CAN
ADC/DAC
APB
ZBT
SSRAM
controller
Control
registers
GPIO B
Stepper B
VIC
System
bus
Address
decoder
Default slave
Unidirectional
to bidirectional
AHB interface
Table 4-1 VHDL file descriptions
File Description
IMAD1fpga This file is the top-level VHDL that instantiates all of the interface for the example. The VHDL for
the PrimeCell interfaces are not supplied but are available from ARM as separate products.
AHBDecoder The decoder provides the AHB peripherals with select line generated from the address lines and the
module ID (position in stack) signals from the motherboard. The Integrator family of boards uses a
distributed address decoding system (see Address assignment of logic modules on page 4-5).
AHBDefaultSlave This block provides a default slave response when the logic module address space is addressed but
the address does not correspond to any of the instantiated peripherals.