ARM IM-AD1 - Manual (Page 51)

Reference Design Example
ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 4-5
Figure 4-2 Integrator system memory map
Note
The Integrator system implements a distributed address decoding scheme in which each
core or logic module is responsible for decoding its own address space. It is important
when implementing a logic module design, to ensure that the module responds to all
memory accesses in the appropriate memory region (see the user guide for your
motherboard).
4.1.4 Address assignment of logic modules
The Integrator motherboards can have more than one logic module mounted on them.
The base address of each logic module depends on its position in the stack and defines
the value of bits [31:28] of the address for all devices on the logic module. Table 4-2 on
APB peripherals
AHB
peripherals
Core module/
motherboard
memory
and peripherals
Core module
alias memory
PCI
Logic module 0
Logic module 1
Logic module 2
Logic module 3
0xC0000000
0xC0000000
0xC1000000
0xCFFFFFFF
0xD0000000
0xE0000000
0xF0000000