ARM IM-AD1 - Manual (Page 71)

Reference Design Example
ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 4-25
The SSP interrupt is the combined interrupt from the SSP PrimeCell. Refer to ARM
PrimeCell Synchronous Serial Port (PL022) Technical Reference Manual for details of
the interrupt sources.
The STEP1, STEP2, STEP3, and STEP4 interrupts are set active when the buffer
registers of the corresponding stepper motor controller are empty. This indicates that a
new step instruction can be written. The interrupts are cleared if the stepper controller
buffer registers are holding a step instruction that is waiting to be carried out.
The CAN1 and CAN2 interrupts are interrupt signals from the CAN controller chips.
The interrupt signals are a combination of interrupts from different sources within the
CAN controller. Refer to the data sheet for the Bosch CC770 for details of the interrupt
sources.
The ADC1 and ADC2 interrupts are generated from the BUSY signal of the
corresponding AD7859 A/D converter chip. The ADC1 and ADC2 interrupts signal that
the ADC has finished its conversion and the value can be read. The interrupt is set active
when the BUSY signal falls at the end of a conversion. The interrupt is cleared by any
read access to the ADC.
Note
The BUSY signal goes active during the power-on calibration of the ADC chips. That
is, the ADC1 and ADC2 interrupts are set after power-on and the interrupts must be
cleared by doing a dummy read access to the ADCs.