Achronix Speedster22i Interlaken - Manual (Page 12)

Clocking
The IIPC has three major clock domains:
1. LBUS clock Domain
• The clk input port is used to clock the protocol processing of the IIPC. This
includes all logic in the TX and RX paths responsible for protocol layer
processing including Control Word, Meta frame and the LBUS interface.
• The frequency of the clk domain is 470MHz
2. RX SerDes clock Domain
• Each SerDes is assumed to provide its recovered clock to the IIPC. These clocks
are connected to the rx_serdes_clk[11:0] input pins and are used to clock the per-
lane logic of each lane. IIPC synchronizes the received data from all of the SerDes
to the LBUS clock domain.
• The frequency of these domains is calculated by simply dividing the serial bit
rate by the parallel bus width (20-bit) of the SerDes block. For example, if the
serial bit rate is 6.25Gbps, the rx_serdes_clk[11:0] will have a frequency of
(6250Mbps/20) = 312.5MHz.
3. TX SerDes Reference Clock Domain
• The TX SerDes domain consists of logic that is operated on the clock domain
associated with each TX SerDes. All of the SerDes must be clocked using the
same reference clock source to ensure frequency matching between the lanes. To
take care of phase differences between lanes, IIPC generates the transmit data for
all SerDes interfaces using one common clock called tx_serdes_refclk.
• The frequency of this domain is calculated by simply dividing the serial bit rate
by the parallel bus width (20-bit) of the SerDes block. For example, if the serial
bit rate is 6.25Gbps, the tx_serdes_refclk will have a frequency of (6250Mbps/20)
= 312.5MHz.
Figure 3 shows the different clock domains in the RX direction along with their associated clock
inputs. Figure 4 shows the different clock domains in the TX direction along with their associated
clock inputs. The IIPC handles all clock domain crossings.
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