Achronix Speedster22i Interlaken - Manual (Page 25)

TX LBUS Interface
The synchronous TX Local bus interface accepts packet oriented data of arbitrary length. It
accepts data in either packet mode, or segment mode. All signals are synchronous relative to the
rising-edge of the clk port. Figure 5 shows a sample waveform for data transaction for a 257 byte
packet.
Figure 5: Sample TX Waveform with a 512-bit Data Bus
Data is written into the interface on every clock cycle when tx_enain is asserted. This signal
qualifies other inputs of the TX Local bus interface. This signal must be valid every clock cycle.
The start of a packet is identified by asserting tx_sopin with tx_enain. The end of a packet is
identified by asserting tx_eopin with tx_enain. Both tx_sopin and tx_eopin may be asserted at the
same cycle. This is done for packets that are less than or equal to the bus width.
The channel number for a packet is presented on the tx_chanin inputs and must be valid for
every cycle tx_enain is asserted. Once tx_sopin has been asserted with a certain channel number,
it may not be asserted again with that channel numbers until tx_eopin is asserted with the same
channel number.
Data is presented on tx_datain inputs. A 512-bit wide bus is used, with the first byte of the packet
is written on bits [511:504], the second byte on bits [503:496], and so forth.
During the last cycle of a packet tx_mtyin signals may be asserted. These signals indicate how
many byte lanes in the data bus are invalid (or empty). tx_mtyin signals only have meaning
during cycles when both tx_enain and tx_eopin are asserted.
If tx_mtyin has a value of 0x0, there are no empty byte lanes, or in other words, all bits of the data
bus are valid. If tx_mtyin has a value of 0x1, then 1 byte lane is empty, specifically bits [7:0] do
not contain valid data. If tx_mtyin has a value of 0x2, then 2 byte lanes are empty, specifically bits
[15:0] do not contain valid data. If tx_mtyin has a value of 0x3, then 3 byte lanes are empty,
specifically bits [23:0] do not contain valid data.
During the last cycle of a packet, when tx_eopin is asserted with tx_enain, tx_errin may also be
asserted. This marks the packet as being in error and this information is included in the final
Interlaken Control Word associated with this packet. When tx_eopin and tx_errin are sampled as
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