Achronix Speedster22i Interlaken - Manual (Page 13)

Figure 3: RX Clock Domains
hs_if per_lane_rx
rx_destriping
clk
serDes
IIPC Core
hs_if per_lane_rx serDes
hs_if per_lane_rx serDes
hs_if per_lane_rx serDes
hs_if per_lane_rx serDes
hs_if per_lane_rx serDes
hs_if per_lane_rx serDes
hs_if per_lane_rx serDes
hs_if per_lane_rx serDes
hs_if per_lane_rx serDes
hs_if per_lane_rx serDes
hs_if per_lane_rx serDes
Interface to user logic in the FPGA Core
rx_serdes_clk[0]
rx_serdes_clk[1]
rx_serdes_clk[2]
rx_serdes_clk[3]
rx_serdes_clk[4]
rx_serdes_clk[5]
rx_serdes_clk[6]
rx_serdes_clk[7]
rx_serdes_clk[8]
rx_serdes_clk[9]
rx_serdes_clk[10]
rx_serdes_clk[11]
UG032, May 15, 2014 13