Document Outline

• Revision History
• Imprint
• Copyright
• Table of Contents
• List of Tables
• List of Figures
• Proprietary Note
• Trademarks
• Environmental Protection Statement
• Explanation of Symbols
• For Your Safety
  • High Voltage Safety Instructions
  • Special Handling and Unpacking Instructions
• General Instructions on Usage
• Two Year Warranty
• 1. Introduction
  • 1.1 Board Overview
    • 1.1.1 Board Introduction
    • 1.1.2 Board Specific Information
  • 1.2 System Relevant Information
    • 1.2.1 System Configuration
    • 1.2.2 Operating Software
  • 1.3 Board Diagrams
    • 1.3.1 Application System Interfacing
    • 1.3.2 System Level Interfacing
    • 1.3.3 Board Layout
  • 1.4 Technical Specifications
  • 1.5 Applied Standards
  • 1.6 Related Publications
• 2. Functional Description
  • 2.1 General Information
  • 2.2 Board-Level Interfacing Diagram
  • 2.3 EB8541 E·Brain™ Module Interfaces
    • 2.3.1 System Interface
    • 2.3.2 System Interface Extension
    • 2.3.3 Communications Interface
    • 2.3.4 Communications Interface Extension
  • 2.4 VMP3 Board Interfaces
    • 2.4.1 J10 – VME Interface
    • 2.4.2 J5A/B – Dual Gigabit Ethernet Interface
    • 2.4.3 J6 – Fast Ethernet Interface
    • 2.4.4 J7 Terminal Interface
    • 2.4.5 J8 JTAG/Debug Interface
    • 2.4.6 J9 PCI Expansion Interface
    • 2.4.7 J11 I/O Expansion Interface
    • 2.4.8 J12 In-System-Programming Interface
• 3. Installation
  • 3.1 Hardware Installation
    • 3.1.1 Safety Requirements
    • 3.1.2 Installation Procedures
    • 3.1.3 Removal Procedures
  • 3.2 Software Installation
• 4. Configuration
  • 4.1 Board Address Map
  • 4.2 Board Control Registers
    • 4.2.1 Board ID Register
    • 4.2.2 Software Compatibility ID
    • 4.2.3 Memory Configuration Register
    • 4.2.4 Control Register
    • 4.2.5 Event Register
    • 4.2.6 Interrupt Configuration Register
    • 4.2.7 Device Interrupt Pending Register
    • 4.2.8 Watchdog Control Register
    • 4.2.9 Board Logic / Revision Register
    • 4.2.10 Serial Interrupt Pending 1 Register
    • 4.2.11 Serial Interrupt Pending 2 Register
    • 4.2.12 Serial Interrupt Mask 1 Register
    • 4.2.13 Serial Interrupt Mask 2 Register
    • 4.2.14 Serial Interrupt Polarity 1 Register
    • 4.2.15 Serial Interrupt Polarity 2 Register
    • 4.2.16 Device Disable Register
    • 4.2.17 Delay Timer Control/Status Register
  • 4.3 UART Registers Address Mapping
    • 4.3.1 UART A (SER1)
    • 4.3.2 UART B (SER2)
    • 4.3.3 UART C (SER3)
    • 4.3.4 UART D (SER4)
  • 4.4 Real-time Clock
  • 4.5 IRQ Routing
  • 4.6 CompactFlash
  • 4.7 EEPROM
  • 4.8 Digital Temperature Sensor, LM75
  • 4.9 Ethernet PHY Addresses
• 5. NetBootLoader
  • 5.1 General Operation
  • 5.2 NetBootLoader Interfaces
    • 5.2.1 MC1 (Abort) Signal
    • 5.2.2 TERM Serial Interface
    • 5.2.3 SER0 Serial Interface
    • 5.2.4 Ethernet Port FCC1 (FE) Interface
  • 5.3 NetBootLoader Functions
    • 5.3.1 NetBootLoader Control
    • 5.3.2 System Status Monitoring
    • 5.3.3 Network Accessing
    • 5.3.4 FLASH Operation
    • 5.3.5 Motorola S-Records
  • 5.4 Operating the NetBootLoader
    • 5.4.1 Initial Setup
    • 5.4.2 Accessing the NetBootLoader
    • 5.4.3 NetBootLoader Configuration
    • 5.4.4 telnet Login
    • 5.4.5 FLASH Operations
    • 5.4.6 Updating the NetBootLoader
    • 5.4.7 Updating With an Image Loaded Via an ftp Server
    • 5.4.8 Uploading a FLASH Area
  • 5.5 Plug and Play
  • 5.6 Porting an Operating System to the CPU Board
  • 5.7 Commands
• 6. System Considerations
  • 6.1 Thermal Design Considerations
    • 6.1.1 Thermodynamics Terminology
    • 6.1.2 System Environment
  • 6.2 Heat Sinks
  • 6.3 Power Considerations
    • 6.3.1 System Power
    • 6.3.2 VMP3 Voltage Ranges
    • 6.3.3 Backplane Requirements
    • 6.3.4 Power Supply Units
    • 6.3.5 Power Consumption of the VMP3
  • 6.4 Start-Up Current of the VMP3
• A. WDOG Functionality
• B. VMP1-IO1 Module
  • B.1 Overview
  • B.2 Board Interfaces
    • B.2.1 PCI Expansion Connector
    • B.2.2 PMC Interface
    • B.2.3 Power Supply
  • B.3 Board Layout
  • B.4 VMP1-IO1 Front Panel
  • B.5 Technical Specifications
  • B.6 Board Installation
  • B.7 Pinouts
    • B.7.1 Jn1 (CON4) Pin Assignment
    • B.7.2 Jn2 (CON5) Pin Assignment
  • B.8 Jumper Setting
• C. VMP1-HDD1 Module
  • C.1 Board Description