ADLINK cExpress-BL - Manual (Page 16)

Page 16 cExpress-BL
3.3 AB Signal Descriptions
3.3.1 Audio Signals
Signal Pin # Description I/O PU/PD Comment
AC_RST# /
HDA_RST# A30 Reset output to codec, active low. O 3.3VSB VSB because PCH uses suspend
power for RESET
AC_SYNC /
HDA_SYNC A29 Sample-synchronization signal to the codec(s). O 3.3V
AC_BITCLK /
HDA_BITCLK A32 Serial data clock generated by the external
codec(s). I/O 3.3V
AC _SDOUT /
HDA_SDOUT A33 Serial TDM data output to the codec. O 3.3V
AC _SDIN[2:0]
HDA_SDIN[2:0] B28
B30 Serial TDM data inputs from up to 3 codecs. I/O 3.3VSB No AC/HAD_SDIN 2 support on
this platform
3.3.2 Analog VGA
Signal Pin # Description I/O PU/PD Comment
VGA_RED B89 Red for monitor.
Analog DAC output, designed to drive a
37.5-Ohm equivalent load. O Analog Not supported
VGA_GRN B91 Green for monitor
Analog DAC output, designed to drive a
37.5-Ohm equivalent load. O Analog Not supported
VGA_BLU B92 Blue for monitor.
Analog DAC output, designed to drive a
37.5-Ohm equivalent load. O Analog Not supported
VGA_HSYNC B93 Horizontal sync output to VGA monitor O 3.3V Not supported
VGA_VSYNC B94 Vertical sync output to VGA monitor O 3.3V Not supported
VGA_I2C_CK B95 DDC clock line (I²C port dedicated to identify
VGA monitor capabilities) I/O OD 3.3V Not supported
VGA_I2C_DAT B96 DDC data line. I/O OD 3.3V Not supported