Echelon Mini FX - Manual (Page 117)

104 Appendix A: Glossary
can be a standard configuration property type (SCPT) or a user-defined configuration
property type (UCPT)
Neuron 5000 Processor
Echelon’s next-generation Neuron chip designed for the L
ON W ORKS 2.0 platform. The
Neuron 5000 processor is faster, smaller, and cheaper that previous-generation Neuron
chips. The Neuron 5000 processor includes a fourth processor for interrupt service
routine (ISR) processing.
The Neuron 5000 processor supports an internal system clock speed of 5 MHz to 80 MHz
(using a 10 MHz external crystal). The Neuron 5000 processor includes 16KB of on-chip
ROM to store the Neuron firmware image and 64 KB on-chip RAM (44 KB is
user-accessible). The Neuron 5000 processor requires at least 2KB of off-chip EEPROM
to store configuration data, and you can use a larger capacity EEPROM device or an
additional flash device (up to 64KB) to store your application code, configuration data,
and an upgradable Neuron firmware image. The Neuron 5000 processor supports the
mapping of external non-volatile memory from 0x4000 to 0xE7FF in the Neuron address
space (a maximum of 42KB).
Neuron Assembler (NAS)
A component of the Neuron C development tools that is used to translate Neuron
Assembly source, such as the code generated from your Neuron C application by the
Neuron C Compiler, into Neuron object code.
Neuron C
A programming language based on ANSI C that you can use to develop applications for
Neuron Chips and Smart Transceivers. It includes network communication, I/O,
interrupt-handling, and event-handling extensions to ANSI C, which make it a powerful
tool for the development of L
ON
W
ORKS
device applications.
Neuron Chip
A semiconductor component specifically designed for providing intelligence and
networking capabilities to low-cost control devices. The Neuron Chip includes a
communication port for connections to various network types.
Neuron Core
The Neuron core includes up to four processors that provide both communication and
application processing capabilities. Two processors execute the layer 2 through 6
implementation of the ISO/IEC 14908-1 Control Network Protocol and the third executes
layer 7 and the application code. Series 5000 chips include a fourth processor for
interrupt service routine (ISR) processing.
Neuron C Compiler (NCC)
A Neuron C tool that is used to produce Neuron assembly code from Neuron C source
code.
Neuron Exporter (NEX)
A component of the Neuron C development tools that takes input from the Neuron C
compiler and the linker and produces the following types of files: downloadable
application image files (.APB, .NDL, and .NXE extensions), programmable application
image files (.NRI, .NFI, .NEI, .NME, and .NMF, extensions), and device interface files
(.XIF and .XFB extensions).