Echelon Mini FX - Manual (Page 20)

Mini FX User's Guide 7
The PL 3150 EVB is a complete L ON W ORKS device that includes a PL 3150 Smart
Transceiver operating at 10MHz external clock (5MHz system clock speed), 64KB of
off-chip flash memory, and 2KB of on-chip RAM.
You can attach a Mini Gizmo I/O Board to the PL 3150/PL 3170 EVBs to test your device
applications and test the example applications included with the Mini FX/PL Evaluation
Kit.
Neuron C Version 2.2 Enhancements
The new features in the Neuron C Version 2.2 programming language include interrupt
support, non-constant device-specific configuration properties, new and enhanced I/O
models, and new and enhanced compiler directives. These new features are detailed in
the Neuron C Programmer’s Guide and Neuron C Reference Guide.
Interrupt Support
The Series 5000 chips support hardware user interrupts in addition to the support
provided through I/O models. The Neuron C Version 2.2 language includes new
keywords to manage hardware user interrupts and a semaphore for application
programs. The Series 5000 chips support the following three types of interrupts: I/O
interrupts, timer/counter driven interrupts, and periodic system interrupts.
When the Series 5000 chips are running at a system clock rate of 20 MHz or greater,
these interrupts execute in the separate interrupt processor on the chips, which improves
the performance of the interrupt and the device application.
Non-Constant Device-Specific Configuration Property
Support
The Neuron C Version 2.2 language supports non-constant device-specific configuration
properties. Non-constant device-specific configuration properties have values that can be
modified by the device application, an LNS network tool such as the LonMaker
®
Integration Tool, or another tool not based on LNS. For example, a thermostat may
include a user interface that allows the user to change the setpoint.
New and Enhanced I/O Models
The Neuron C Version 2.2 language now includes support for the stretched triac output
model, and it includes some enhancements to the existing SCI and I2C I/O models.
The stretched triac output model provides improved control when driving inductive
loads. The stretched triac model requires a Neuron 5000 Processor.
The SCI input/output model now supports a configurable parity bit (none, even, odd).
The parity feature requires a Series 5000 chip even though the SCI model is available on
some Series 3100 chips.
The I2C input/output model now supports slow and fast operation speeds for compliance
with the I2C standard when operating at very high system clock speeds.
New and Enhanced Compiler Directives
The Neuron C Version 2.2 language includes new compiler directives and existing
compiler directives that have been enhanced to help you develop location-independent
and modular code.