Altera LVDS SERDES - Manual (Page 14)

Description Value Parameter
When enabled, the Altera LVDS SERDES IP core
drives the
rx_dpa_locked
signal low when the DPA
changes phase selection from the initially locked
position. The Altera LVDS SERDES IP core drives
the
rx_dpa_locked signal high if the DPA changes
the phase selection back to the initial locked
position.
When disabled, the Altera LVDS SERDES IP core
drives the
rx_dpa_locked
signal low when the DPA
moves two phases in the same direction away from
the initial locked position. The Altera LVDS
SERDES IP core drives the
rx_dpa_locked
signal
high if the DPA changes the phase selection to be
within one phase or same phase as the initial locked
position.
A de-assertion of rx_dpa_locked does not indicate
the data is invalid, it indicates the DPA has changed
phase taps to track variations between the inclock
and
rx_in
data. Altera recommends using data
checkers to verify data accuracy.
— Enable DPA loss of lock on one
change
When enabled, DPA logic counts the rising edges
on the incoming serial data only. When disabled,
DPA logic counts the rising and falling edges.
This port is only recommended for use
in high jitter systems, and Altera
recommends disabling this port in
typical applications. Note:
— Enable DPA alignment only to
rising edges of data
Specifies the amount of phase drift the ALTERA_
LVDS simulation model should add to the
recovered
rx_divfwdclks .
This feature is not supported in the
current version of the Quartus II
software. Note:
— (Simulation only) Specify PPM drift
on the recovered clock(s)
Non-DPA Settings
Specifies the ideal phase delay of the inclock with
respect to transitions in the incoming serial data in
degrees of the LVDS fast clock. For example,
specifying 180 degrees implies the inclock is center
aligned with the incoming data. — Desired receiver inclock phase shift
(degrees):
Altera LVDS SERDES IP Core User Guide Altera Corporation
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Receiver Settings Tab 14
2014.08.18