Altera LVDS SERDES - Manual (Page 24)

Timing Closure
Timing Violation in Internal FPGA Paths
An LVDS SERDES design with high frequency and low SERDES factor is prone to have challenges at closing
timing at internal FPGA paths.
If setup violation is observed, consider the following guidelines:
• If setup violation from core registers to LVDS TX hardware is reported, check the TX core registers
clock parameter. If it is set to inclock, consider changing to tx_coreclock. Core registers using tx_coreclock
have less clock delay because of the PLL compensation delay on the tx_coreclock path. This can result
in less source clock delay which gives more setup slack to such transfer.
• However, if the TX core registers clock parameter is set to tx_coreclock, consider lowering the data rate
or increasing the SERDES factor to reduce the core frequency requirement and to provide more setup
slack.
If hold violation from LVDS RX to core registers is observed, consider the following guideline:
• Check the setup slack for such transfer. If there is ample setup slack, you may attempt to over-constraint
the hold for such transfer. Under normal circumstances, the Fitter should try to fix hold violation by
adding delay. It is possible that the Fitter may think adding more delay to avoid hold violation at the fast
corner will hurt setup at the slow corner.
Design Example
The Altera LVDS SERDES IP core can generate a design example that matches the same configuration chosen
for the IP core. The design example is a simple design that does not target any specific application; however
you can use the design example as a reference on how to instantiate the IP core and what behavior to expect
in a simulation.
Generating Design Example
During generation, the Generation dialog box displays the option to generate a design example. Turn on
the Generate Example Design option.
The software generates the <instance>_example_design directory along with the IP core, where <instance>
is the name of your IP core.
The <instance>_example_design directory contains two TCL scripts:
•
- make_qii_design.tcl
•
- make_sim_design.tcl
Generating Quartus Design Example
The
make_qii_design.tcl
generates a synthesizable design example along with a Quartus project, ready
for compilation.
To generate synthesizable design example, run the following script at the end of IP generation:
quartus_sh -t make_qii_design.tcl
Altera LVDS SERDES IP Core User Guide Altera Corporation
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Timing Closure 24
2014.08.18