Altera User Flash Memory User Manual
Page 14
Description
Configuration Setting
Specify the device family that you want to use.
Which device family will you be
using?
You can choose AHDL(.tdf), VHDL(.vhd), or Verilog HDL (.v) as the
output file type.
Which type of output file do
you want to create?
Specify the name of the output file.
What name do you want for the
output file?
Turn on this option if you want to return to this page to create multiple IP
cores.
Return to this page for another
create operation
Specifies the device family you chose on page 2a.
Currently selected device family
Turn on this option to ensure that the device selected matches the device
family that is chosen in the previous page.
Match project/default
Turn on this option to enable the arclkena port.
Use ‘arclkena’ output port
Turn on this option to enable drclkena port.
Use ‘drclkena’ input port
• Select Initialize blank memory if you do not want to specify any initial-
ization file. Select Initialize from hex or mif file to specify the initializa-
tion file. Type the file name or browse for the required file.
• In the Quartus II software, the memory content values from your .hex
or .mif are hard-coded into your ALTUFM IP core variation file when
you generate the IP variation. If you change the contents of your .hex
or .mif after generating the IP variation, these updates will not be
reflected in simulation. This may cause a mismatch between simulation
and device behavior because compilation and program file generation
in the Quartus II software use the current .hex or .mif contents instead
of the hard-coded values.To avoid this mismatch, regnenerate the
ALTUFM IP core whenever you update your .hex or .mif.
Memory content initialization
Specify the oscillator frequency for the user flash memory. This parameter
is used for simulation purposes only. The values are 5.56MHz and 3.33MHz.
If omitted, the default is 5.56MHz.
Oscillator frequency
Specify the erase time.
Erase time
Specify the program time.
Program time
Turn on this option if you want to generate a netlist for your third-party
EDA synthesis tool to estimate the timing and resource usage of the IP core.
If you turn on this option, a netlist file (_syn.v) is generated. This file is a
representation of the customized logic used in the Quartus
II software and provides the connectivity of the architectural elements in
the IP core but may not represent true functionality.
Generate netlist
Altera User Flash Memory (ALTUFM) IP Core User Guide
Altera Corporation
UG-040105
Parameter Settings
14
2014.08.18