Altera User Flash Memory - Manual (Page 25)

Asserting READ, WRITE, and ERASE at the same time is not allowed. Multiple requests are ignored and
nothing is read from, written to, or erased in the UFM block. There is no support for sequential read and
page write in the parallel interface.
Even though the altufm IP core allows you to select the address widths range from 3 bits to 9 bits, the UFM
block always expects full 9 bits width for the address register. Therefore, the ALTUFM IP core always pads
the remaining LSB of the address register with ‘0’s if the register width selected is less than 9 bits. The address
register will point to sector 0 if the address received at the address register starts with a ‘0’. On the other
hand, the address register will point to sector 1 if the address received starts with a ‘1’.
Even though you can select an optional data register width of 3 to 16 bits using the altufm IP core, the UFM
block always expects full 16 bits width for the data register. Reading from the data register will always proceed
from MSB to LSB. The altufm IP core will always pad the remaining LSB of the data register with 1s if the
user selects a data width of less than 16-bits.
During the read/write mode, a high-to-low transition of a mode signal (nREAD, nWRITE, or nERASE)
requires a minimum of 420 ns of hold time before the instruction signal can be pulled high again. The address
register and data input must be held for at least 420 ns once the mode signal is asserted low. The high-to-
low transition of nBUSY requires a maximum wait of 210 ns once nRead, nWrite, or nErase is asserted low.
I2C Interface
The inter-integrated circuit (I2C) is a bidirectional two-wire interface protocol. Choose this interface to
configure the UFM block and logic as a slave device for the I2C bus. The size of UFM memory, the access
mode, the erase method, and the protection required for the UFM block all dictate the resources required
on a particular device for this interface implementation.
For more information about using the ALTUFM IP core with the I2C interface, refer to AN489: Using the
UFM in MAX II Devices.
None (Altera Serial Interface)
None means using the dedicated UFM serial interface. The built-in UFM interface uses 13 pins for the
communication. You can produce your own interface design to communicate to/from the dedicated UFM
interface and implement it in the logic array.
Common Applications
The MAX II and MAX V UFM block is the best choice for storing manufacturing data, helping to improve
board space efficiency, and minimizing system cost by integrating board-level flash memory, EEPROM
capabilities, and system logic into one device. You can customize the UFM communication system to comply
with different manufacturers’ standard interface protocols to access manufacturing product data.
The UFM block is used to replace on-board flash and EEPROM memory devices which are used to store
ASSP or processor configuration bits, or electronic ID information for a board during manufacturing. Since
you can program the UFM block to suit your needs, MAX II and MAX V devices offer more interface
flexibility than an off-the-shelf EEPROM device.
Design Example: User Flash Memory with SPI Interface
This design example uses the ALTUFM IP core to implement user flash memory with the SPI Interface using
the parameter editor in the Quartus II software.
Altera Corporation Altera User Flash Memory (ALTUFM) IP Core User Guide
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25 I2C Interface
UG-040105
2014.08.18