Altera Nios II Embedded Evaluation Kit Cyclone III Edition User Manual
Page 30
Altera Corporation
Development Board Version 1.0.
3–6
July 2010
Nios II Embedded Evaluation Kit, Cyclone III Edition
Nios II Processor Systems
f
For technical details on the components in standard hardware system
refer to
Communication Interfaces
There are several communication interfaces included in the Nios II
Standard System:
■
JTAG UART
—
Used for Serial communication and debugging Nios
II applications via the on-board USB-Blaster circuitry.
■
UART
—
Serial communication link for general purpose
communications and debug.
■
SPI
—
Used to communicate with the touch panel portion of the LCD
Touchscreen.
■
10/100 Ethernet Controller
—
The Ethernet controller uses the
Triple-speed Ethernet MAC to communicate with the PHY on the
LCD Multimedia Daughtercard.
■
Video Pipeline
—
The video pipeline outputs the appropriate pixel
data and sync signals to the LCD Touch Panel. It provides high
bandwidth memory access that allows for flicker free display on the
color LCD. A more detailed description of the data flow for the video
pipeline can be found in
.
The video pipeline is comprised of:
●
PIO for LCD I
2
C Controller
—
The I
2
C pins are used to configure
the LCD panel for brightness and set the gamma correction
curves.
●
SPI Touch Panel Controller
—
Used to communicate with the
touch panel ADCs.
●
Pixel Converter
—
Logic block that converts parallel 32-bit
R-G-B-0 data to an 8-bit data stream. This is required because of
the pin-limitation placed on the system by the HSMC connector.
The video data-stream is multiplexed in the FPGA on the
Cyclone III Starter Board and de-multiplexed in the MAX II
device on the LCD Multimedia Daughtercard.
●
Sync Generator
—
Generates the horizontal and vertical sync
signals for each frame displayed on the LCD touch screen.
f
For more information on the video pipeline (pixel
converter and Video Sync Generator) and GPIO
components refer to
.