Altera Cyclone V E FPGA - Manual (Page 21)

Chapter 6: Board Test System 6–5
Using the Board Test System
December 2014 Altera Corporation Cyclone V E FPGA Development Kit
User Guide
1 If you plug in an external USB-Blaster cable to the JTAG header (J4), the On-Board
USB-Blaster II is disabled.
1 JTAG DIP switch bank (SW2) selects which interfaces are in the chain. Refer to
Table 4–2 on page 4–3 for detailed settings.
f
For details on the JTAG chain, refer to the Cyclone V E FPGA Development Board
Reference Manual. For USB-Blaster II configuration details, refer to the On-Board
USB-Blaster II page.
Qsys Memory Map
The Qsys memory map control shows the memory map of the Qsys system on your
board.